Alternatives and similar repositories for espresso-logic

Users that are interested in espresso-logic are comparing it to the libraries listed below

• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆142Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆106Updated 2 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated last week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆138Updated this week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆144Updated last month
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆194Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆461Updated last week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• phanrahan / magma
  magma circuits
  ☆261Updated 9 months ago
• msoeken / cirkit
  A circuit toolkit
  ☆103Updated 5 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆105Updated 9 years ago
• lsils / mockturtle
  C++ logic network library
  ☆240Updated 3 weeks ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated this week
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆114Updated this week
• rdaly525 / coreir
  ☆103Updated 3 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated last week
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆84Updated last month
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆86Updated last year
• antmicro / sv-bugpoint
  ☆26Updated 3 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 9 months ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• nbulsi / also
  A logic synthesis tool
  ☆74Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆122Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 3 weeks ago