classabbyamp / espresso-logic
A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
☆132Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for espresso-logic
- SystemVerilog synthesis tool☆169Updated this week
- RISC-V Formal Verification Framework☆111Updated last month
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆128Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆135Updated last month
- ☆107Updated 3 years ago
- SystemVerilog frontend for Yosys☆46Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆407Updated 2 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆281Updated 2 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆202Updated last week
- ACT hardware description language and core tools.☆100Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆255Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- A SystemVerilog source file pickler.☆52Updated last month
- CoreIR Symbolic Analyzer☆61Updated 4 years ago
- A Standalone Structural Verilog Parser☆84Updated 2 years ago
- Showcase examples for EPFL logic synthesis libraries☆184Updated 7 months ago
- IDEA project source files☆98Updated 2 weeks ago
- Fabric generator and CAD tools☆148Updated last week
- Builds, flow and designs for the alpha release☆53Updated 4 years ago
- WAL enables programmable waveform analysis.☆138Updated 3 weeks ago
- EPFL logic synthesis benchmarks☆166Updated 2 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆134Updated 5 months ago
- A RISC-V processor in system verilog☆13Updated 4 years ago
- Hardware generator debugger☆71Updated 9 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆60Updated last year
- ☆75Updated last year
- A command-line tool for displaying vcd waveforms.☆47Updated 9 months ago
- Python wrapper for verilator model☆78Updated 9 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆118Updated 5 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago