lowRISC / arianeLinks
Ariane is a 6-stage RISC-V CPU
☆150Updated 6 years ago
Alternatives and similar repositories for ariane
Users that are interested in ariane are comparing it to the libraries listed below
Sorting:
- ☆190Updated last year
- A Fast, Low-Overhead On-chip Network☆250Updated this week
- Vector processor for RISC-V vector ISA☆131Updated 5 years ago
- RISC-V Verification Interface☆129Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- Basic RISC-V Test SoC☆162Updated 6 years ago
- ☆250Updated 2 years ago
- RISC-V System on Chip Template☆159Updated 3 months ago
- Network on Chip Implementation written in SytemVerilog☆195Updated 3 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆288Updated 3 weeks ago
- RISC-V Torture Test☆204Updated last year
- Verilog Configurable Cache☆186Updated last week
- Code used in☆198Updated 8 years ago
- RISC-V Virtual Prototype☆182Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆75Updated last week
- VeeR EL2 Core☆306Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆229Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆303Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- Open-source RISC-V microcontroller for embedded and FPGA applications☆188Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆126Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 2 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- A dynamic verification library for Chisel.☆159Updated last year