lowRISC / ariane
Ariane is a 6-stage RISC-V CPU
☆122Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for ariane
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- RISC-V System on Chip Template☆153Updated this week
- ☆160Updated 10 months ago
- RISC-V Verification Interface☆74Updated 2 months ago
- Verilog Configurable Cache☆167Updated 2 months ago
- Fabric generator and CAD tools☆148Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆90Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆140Updated last year
- VeeR EL2 Core☆252Updated this week
- Instruction Set Generator initially contributed by Futurewei☆264Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 2 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 4 months ago
- SystemVerilog synthesis tool☆168Updated this week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆172Updated this week
- Network on Chip Implementation written in SytemVerilog☆156Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆199Updated 4 years ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆224Updated 2 months ago
- Code used in☆173Updated 7 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆215Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆176Updated 2 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆255Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- CORE-V Family of RISC-V Cores☆206Updated 8 months ago
- An Open-Source Design and Verification Environment for RISC-V☆75Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated this week
- Vector processor for RISC-V vector ISA☆109Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆433Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 4 months ago