Alternatives and similar repositories for ariane:

Users that are interested in ariane are comparing it to the libraries listed below

• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆177Updated 6 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆167Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆156Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆84Updated 4 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆238Updated 2 months ago
• subbdue / systemverilog.io
  Code used in
  ☆177Updated 7 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 7 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆170Updated last month
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆112Updated 4 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆259Updated this week
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆77Updated 3 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆264Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆144Updated 2 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆138Updated 7 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆232Updated 3 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆93Updated 3 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆151Updated last month
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆165Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆156Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆241Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 2 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆222Updated 2 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆451Updated 3 months ago