Alternatives and similar repositories for ariane:

Users that are interested in ariane are comparing it to the libraries listed below

• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆175Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆84Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆272Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆264Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆245Updated 3 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆172Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆206Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 3 months ago
• chipsalliance / uvm-verilator
  ☆87Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆456Updated 2 weeks ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 8 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆162Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆221Updated 3 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆146Updated 3 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆266Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆245Updated 2 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆209Updated 4 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆171Updated 3 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆228Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• SpinalHDL / NaxRiscv
  ☆275Updated this week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆168Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆182Updated 7 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆183Updated 3 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆108Updated 6 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆226Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆167Updated 7 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆159Updated 2 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆112Updated 5 years ago