canaknesil / 4x4-apufLinks
An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
☆15Updated 4 years ago
Alternatives and similar repositories for 4x4-apuf
Users that are interested in 4x4-apuf are comparing it to the libraries listed below
Sorting:
- Ring Oscillator Physically Unclonable Funtion☆23Updated 3 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- ☆20Updated 2 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 5 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Updated 3 months ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 6 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆22Updated 3 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Updated 9 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆132Updated last year
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆34Updated 10 years ago
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- ☆61Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 weeks ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- Basic RISC-V Test SoC☆137Updated 6 years ago
- opensource crypto IP core☆27Updated 4 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Updated 7 years ago
- Verilog based BCH encoder/decoder☆122Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆37Updated 4 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆54Updated 7 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago