Alternatives and similar repositories for 2D-Systolic-Array-Multiplier:

Users that are interested in 2D-Systolic-Array-Multiplier are comparing it to the libraries listed below

• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆42Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆63Updated 3 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆57Updated 11 months ago
• EECS150 / asic_labs_sp22
  ☆22Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆58Updated 5 months ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆40Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆83Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆62Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆90Updated 5 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• bol-edu / caravel-soc_fpga-lab
  ☆16Updated last week
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆56Updated last year
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆30Updated 2 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆69Updated this week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆85Updated last year
• ahmad-mirsalari / PULP
  A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.
  ☆21Updated last year
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆51Updated 4 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 3 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆43Updated 9 months ago
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆30Updated 4 years ago
• matbi86 / 01_ai_accelerator_basic_for_student
  ai_accelerator_basic_for_student (no solve)
  ☆12Updated 5 years ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆38Updated 3 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆56Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 3 weeks ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆51Updated 7 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆97Updated 4 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago