tms4517 / 2D-Systolic-Array-MultiplierLinks
2D Systolic Array Multiplier
☆24Updated 2 years ago
Alternatives and similar repositories for 2D-Systolic-Array-Multiplier
Users that are interested in 2D-Systolic-Array-Multiplier are comparing it to the libraries listed below
Sorting:
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆66Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 3 weeks ago
- Two Level Cache Controller implementation in Verilog HDL☆57Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- ai_accelerator_basic_for_student (no solve)☆14Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆68Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆77Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆267Updated last week
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆59Updated last year
- round robin arbiter☆77Updated 11 years ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆115Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- ☆40Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- ☆70Updated 3 years ago
- ☆22Updated last year