tms4517 / 2D-Systolic-Array-MultiplierLinks
2D Systolic Array Multiplier
☆20Updated last year
Alternatives and similar repositories for 2D-Systolic-Array-Multiplier
Users that are interested in 2D-Systolic-Array-Multiplier are comparing it to the libraries listed below
Sorting:
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆82Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 10 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆77Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 10 months ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated 3 weeks ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 9 months ago
- A Fast, Low-Overhead On-chip Network☆226Updated last month
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆108Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆59Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆46Updated last year
- SystemVerilog Tutorial☆172Updated 4 months ago
- ☆36Updated 6 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated last month
- ☆13Updated 5 months ago
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆116Updated 3 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆53Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- A collection of commonly asked RTL design interview questions☆32Updated 8 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆109Updated last year
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago