tms4517 / 2D-Systolic-Array-MultiplierLinks
2D Systolic Array Multiplier
☆18Updated last year
Alternatives and similar repositories for 2D-Systolic-Array-Multiplier
Users that are interested in 2D-Systolic-Array-Multiplier are comparing it to the libraries listed below
Sorting:
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆174Updated 9 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆170Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆221Updated last month
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆75Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- ☆26Updated 2 years ago
- ☆34Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- Network on Chip Implementation written in SytemVerilog☆189Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆52Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆107Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆62Updated last year
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆135Updated last week
- SystemVerilog Tutorial☆166Updated 3 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆259Updated last month
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- Simple cache design implementation in verilog☆49Updated last year