scluconn / DA_PUF_LibraryLinks
Defense/Attack PUF Library (DA PUF Library)
☆50Updated 5 years ago
Alternatives and similar repositories for DA_PUF_Library
Users that are interested in DA_PUF_Library are comparing it to the libraries listed below
Sorting:
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆22Updated 9 months ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 3 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆31Updated last year
- Cryptanalysis of Physically Unclonable Functions☆87Updated last year
- Repository to store all design and testbench files for Senior Design☆18Updated 5 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆32Updated this week
- ☆21Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆54Updated last week
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- HW Design Collateral for Caliptra RoT IP☆100Updated this week
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆10Updated 5 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated 8 months ago
- Hardware Design of Ascon☆23Updated 3 weeks ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- ☆23Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- SCARV: a side-channel hardened RISC-V platform☆20Updated 4 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆44Updated 5 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 6 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- This script generates and analyzes prefix tree adders.☆38Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago