scluconn / DA_PUF_Library
Defense/Attack PUF Library (DA PUF Library)
☆46Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for DA_PUF_Library
- FPGA implementation of a physical unclonable function for authentication☆32Updated 7 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 6 years ago
- Cryptanalysis of Physically Unclonable Functions☆79Updated 4 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆27Updated 9 months ago
- Repository to store all design and testbench files for Senior Design☆17Updated 4 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆10Updated 4 years ago
- ☆16Updated 4 months ago
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆43Updated last year
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- A list of VHDL codes implementing cryptographic algorithms☆25Updated 2 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated last month
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- Ring Oscillator Physically Unclonable Funtion☆18Updated 3 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆16Updated 2 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆15Updated 5 years ago
- Elgamal's over Elliptic Curves☆19Updated 5 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆12Updated this week
- C++ and Verilog to implement AES128☆16Updated 6 years ago
- ☆12Updated 9 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆14Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- FIPS 202 compliant SHA-3 core in Verilog☆18Updated 4 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆37Updated 7 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆29Updated 4 months ago
- ☆24Updated 3 months ago
- ☆20Updated 5 years ago
- The ML_Attack_XOR_PUF is a Machine Learning-based model for attacking the XOR Physical Unclonable Functions using a small number of chall…☆16Updated 4 years ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago