Alternatives and similar repositories for DA_PUF_Library

Users that are interested in DA_PUF_Library are comparing it to the libraries listed below

• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆36Updated last year
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆21Updated 5 years ago
• nils-wisiol / pypuf
  Cryptanalysis of Physically Unclonable Functions
  ☆91Updated last year
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆23Updated 8 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆27Updated 4 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 8 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆40Updated last month
• aneeshkandi14 / ascon-hw-public
  ☆21Updated last year
• KULeuven-COSIC / NTRU_NTT_HW
  ☆25Updated 4 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆11Updated 6 years ago
• ascend-secure-processor / oram
  Hardware implementation of ORAM
  ☆24Updated 8 years ago
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆29Updated 2 months ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆136Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated last week
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆17Updated 6 years ago
• ucb-bar / sha3
  ☆81Updated last year
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆23Updated 5 years ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆12Updated 5 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆78Updated 5 years ago
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆15Updated 8 years ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated last month
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆19Updated 6 years ago
• KULeuven-COSIC / HEAT
  Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)
  ☆63Updated 5 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆95Updated last year
• alibaba-damo-academy / damo_ctl_cham
  ☆26Updated 2 years ago