scluconn / DA_PUF_LibraryLinks
Defense/Attack PUF Library (DA PUF Library)
☆50Updated 5 years ago
Alternatives and similar repositories for DA_PUF_Library
Users that are interested in DA_PUF_Library are comparing it to the libraries listed below
Sorting:
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆32Updated last year
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 7 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆22Updated 10 months ago
- Repository to store all design and testbench files for Senior Design☆19Updated 5 years ago
- Cryptanalysis of Physically Unclonable Functions☆88Updated last year
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 3 years ago
- Side-channel analysis setup for OpenTitan☆35Updated 2 weeks ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Ring Oscillator Physically Unclonable Funtion☆24Updated 3 years ago
- ☆81Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆55Updated last month
- Hardware implementation of ORAM☆22Updated 8 years ago
- ☆21Updated last year
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- HW Design Collateral for Caliptra RoT IP☆103Updated this week
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆11Updated 5 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆22Updated 4 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆136Updated last year
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆33Updated this week
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 6 years ago
- VHDL Implementation of AES Algorithm☆82Updated 4 years ago
- This script generates and analyzes prefix tree adders.☆39Updated 4 years ago
- ☆24Updated 3 years ago
- Hardware Design of Ascon☆23Updated 2 weeks ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year