Alternatives and similar repositories for MicroScope:

Users that are interested in MicroScope are comparing it to the libraries listed below

• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆19Updated 4 years ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆59Updated 4 years ago
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆30Updated last year
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• vusec / tlbdr
  ☆18Updated 2 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• sectrs-acai / acai
  Protecting Accelerator Execution with Arm Confidential Computing Architecture (USENIX Security 2024)
  ☆26Updated last year
• FxPiGaAo / Hacky-Racer
  ☆16Updated last year
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆14Updated 5 years ago
• Secure-AI-Systems-Group / Mastik
  GitHub (mirror) repository for the Mastik toolkit, written by Yuval Yarom https://cs.adelaide.edu.au/~yval/Mastik/
  ☆37Updated 5 years ago
• fanyao / branchspec
  Proof of concept code for the BranchSpec exploit.
  ☆9Updated 2 years ago
• Miro-H / CacheSC
  Library for Prime+Probe cache side-channel attacks on L1 and L2
  ☆31Updated 4 years ago
• flowyroll / uarchsec
  ☆44Updated 6 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆26Updated 4 years ago
• zzrcxb / LLCFeasible
  Open source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆21Updated 4 months ago
• efeslab / dolma
  ☆12Updated 4 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆44Updated 5 years ago
• nagnagnet / PrimeProbe
  ☆18Updated 6 years ago
• jasonyu1996 / elasticlave
  ☆23Updated 2 weeks ago
• cwfletcher / stt
  ☆35Updated 4 years ago
• nepoche / Flush-Reload
  A flush-reload side channel attack implementation
  ☆45Updated 2 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• ahoi-attacks / WeSee
  Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)
  ☆24Updated 11 months ago
• PittECEArch / AdversarialPrefetch
  ☆19Updated 2 years ago
• KULeuven-COSIC / ShowTime
  Artifacts for our ShowTime paper (AsiaCCS '23), including distinguishing cache hits and misses with the human eye.
  ☆12Updated last year
• proteus-core / prospect
  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
  ☆16Updated 4 months ago
• cispa / mwait
  Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…
  ☆25Updated last year
• eepalms / gem5-newcache
  New Cache implementation using Gem5
  ☆13Updated 10 years ago