dskarlatos / MicroScopeLinks
Microscope: Enabling Microarchitectural Replay Attacks
☆19Updated 5 years ago
Alternatives and similar repositories for MicroScope
Users that are interested in MicroScope are comparing it to the libraries listed below
Sorting:
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 2 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆48Updated 6 years ago
- Protecting Accelerator Execution with Arm Confidential Computing Architecture (USENIX Security 2024)☆26Updated last year
- ☆23Updated 4 months ago
- The open-source component of Prime+Scope, published at CCS 2021☆34Updated 2 years ago
- ☆110Updated 2 years ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆26Updated 4 months ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆23Updated last year
- ☆25Updated 2 months ago
- ☆45Updated 6 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆61Updated 2 years ago
- ☆35Updated 4 years ago
- ☆18Updated 2 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).☆40Updated 2 years ago
- ☆22Updated 2 years ago
- ☆16Updated last month
- ☆49Updated 3 years ago
- HW interface for memory caches☆28Updated 5 years ago
- Reload+Refresh PoC☆15Updated 5 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- Library for Prime+Probe cache side-channel attacks on L1 and L2☆35Updated 5 years ago
- ☆32Updated 2 years ago
- Proof of concept code for the BranchSpec exploit.☆9Updated 3 years ago
- SGXBounds: Memory Safety for Shielded Execution (compiler pass and runtime)☆33Updated 8 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆21Updated 2 years ago
- ☆23Updated 3 years ago
- A flush-reload side channel attack implementation☆52Updated 3 years ago