This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL
☆29Oct 4, 2021Updated 4 years ago
Alternatives and similar repositories for HLS-Tiny-Tutorials
Users that are interested in HLS-Tiny-Tutorials are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Miscellaneous things and projects for my ZYBO and ZYNQ devices.☆11Aug 30, 2023Updated 2 years ago
- A collection of Opal Kelly provided design resources☆18Nov 7, 2025Updated 5 months ago
- ☆13Apr 15, 2025Updated last year
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- ☆11Feb 5, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V Integrated Matrix Development Repository☆23Updated this week
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- A toolkit for interactive visualization of signal and image processing on Jupyter Notebooks.☆11Mar 31, 2022Updated 4 years ago
- rv6 is a kernel & operating system written entirely in rust.☆11Nov 7, 2019Updated 6 years ago
- ☆11Feb 28, 2016Updated 10 years ago
- Posit Arithmetic Cores generated with FloPoCo☆29Jun 25, 2024Updated last year
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- Vitis Video Analytics SDK☆46Apr 25, 2024Updated 2 years ago
- Code for the "Rendering 3D Graphics On An Oscilloscope" video☆14Mar 8, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆205Nov 14, 2021Updated 4 years ago
- Benchmarks for High-Level Synthesis☆10Mar 17, 2023Updated 3 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆29Mar 24, 2021Updated 5 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- Digital circuit simulator, written by Jeffery P. Hansen☆10Aug 29, 2019Updated 6 years ago
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- A Synthesizable implementation of H.264 Video Decoding☆36Mar 2, 2016Updated 10 years ago
- ☆11Apr 15, 2024Updated 2 years ago
- Simple Memory Allocation Simulator. (Python)☆13May 7, 2023Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆10Nov 3, 2020Updated 5 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- ☆15Nov 12, 2023Updated 2 years ago
- An indoor positioning system relying on time difference of arrival measurements of ultrasonic pings from fixed transmitters.☆11May 15, 2015Updated 10 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated last year
- RCP over DDS C++ API☆13Jan 27, 2016Updated 10 years ago
- Accelerate convolution neural network for face recognition using GPU☆14Nov 24, 2020Updated 5 years ago
- SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs☆19May 23, 2024Updated last year
- SystemVerilog IPs and Modules for architectural redundancy designs.☆20Apr 16, 2026Updated 2 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Edge Impulse firmware for Nordic Thingy91☆13Apr 3, 2026Updated 3 weeks ago
- Uvvy peer-to-peer communication and sharing client☆28Apr 25, 2018Updated 8 years ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆23Aug 13, 2025Updated 8 months ago
- Example project that uses the AXI DMA peripheral to connect a custom AXI-Stream peripheral to memory☆14Feb 28, 2014Updated 12 years ago
- A port from Arjo's uSpeech library (originally intended for Arduino)☆14Jan 6, 2016Updated 10 years ago
- Branches contain some experiments. lkmc-* branches are for: https://github.com/cirosantilli/linux-kernel-module-cheat☆12Mar 13, 2022Updated 4 years ago
- Open-channel SSD on Cosmos-plus OpenSSD☆24Sep 11, 2018Updated 7 years ago