Alternatives and similar repositories for HLS-Tiny-Tutorials:

Users that are interested in HLS-Tiny-Tutorials are comparing it to the libraries listed below

• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆42Updated 2 months ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆28Updated 4 years ago
• ATaylorCEngFIET / Vitis_Hero
  ☆24Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆50Updated 2 weeks ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆51Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆67Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated 2 months ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆36Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆58Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆70Updated 8 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆59Updated 5 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆72Updated 3 weeks ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆99Updated last year
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated last year
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆73Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆48Updated 2 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• kmanev / ZynqUSp-AXI-Speedtest
  ☆14Updated 5 years ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆80Updated 4 months ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆24Updated 3 years ago
• VeriGOOD-ML / public
  ☆56Updated last year
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• chipsalliance / uvm-verilator
  ☆88Updated last year
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆27Updated 4 years ago