Computer-Aided VLSI System Design
☆25Oct 24, 2024Updated last year
Alternatives and similar repositories for NTU_CVSD_2021
Users that are interested in NTU_CVSD_2021 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Professor: C.H. Yang☆10Aug 16, 2025Updated 8 months ago
- 丁建均老師的"時頻分析和小波轉換"作業(TFW)☆11Jan 18, 2024Updated 2 years ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- ☆14Feb 13, 2022Updated 4 years ago
- Hardware Description Language on FPGA☆10Sep 18, 2023Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- 紀錄一下自己寫過的所有Lab☆38Jan 18, 2024Updated 2 years ago
- ☆33Jan 6, 2026Updated 4 months ago
- Instruction and files for porting Arm DesignStart to CW305.☆17Dec 6, 2023Updated 2 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆16Mar 12, 2023Updated 3 years ago
- A simple implementation of LoRA+: Efficient Low Rank Adaptation of Large Models☆10Mar 20, 2024Updated 2 years ago
- ☆37Sep 17, 2024Updated last year
- 黃鐘揚老師的"系統晶片驗證"作業與專題(SoCV)☆10Jan 18, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆43Apr 6, 2023Updated 3 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- RTL to GDS via Cadence Tools☆17May 17, 2022Updated 3 years ago
- 交大電子所-積體電路實驗設計-李鎮宜教授☆14Sep 4, 2024Updated last year
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- ☆24Mar 20, 2025Updated last year
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated last year
- ☆70Apr 7, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 108下 計算機組織 Computer Organization 李毅郎☆11Feb 22, 2021Updated 5 years ago
- Code for generating config files for ESIM Multi-Object-2D simulator☆26Mar 5, 2022Updated 4 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 9 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- ☆14Jan 4, 2023Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- PSA-ADAC SDC-600 Secure Debug Manager library for authenticated debug☆16Mar 18, 2025Updated last year
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆35Sep 21, 2023Updated 2 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆203Apr 2, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆22Apr 2, 2023Updated 3 years ago
- Verilog implementation of a ultrasonic radar☆19Jan 7, 2018Updated 8 years ago
- a Computing In Memory emULATOR framework☆15May 19, 2024Updated last year
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- ☆16Dec 12, 2020Updated 5 years ago
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆29Aug 15, 2025Updated 8 months ago
- Code related to the ELM neuron.☆15Feb 27, 2024Updated 2 years ago