albertfan1120 / NTU_CVSD_2021Links
Computer-Aided VLSI System Design
☆21Updated 10 months ago
Alternatives and similar repositories for NTU_CVSD_2021
Users that are interested in NTU_CVSD_2021 are comparing it to the libraries listed below
Sorting:
- ☆14Updated 4 years ago
- IC Contest☆39Updated 2 years ago
- 交通大學iclab 2023 fall☆33Updated 10 months ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆21Updated last year
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆129Updated 11 months ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆13Updated 2 years ago
- ☆38Updated 2 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆91Updated 4 months ago
- ☆38Updated 2 years ago
- 紀錄一下自己寫過的所有Lab☆33Updated last year
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- ☆13Updated 3 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆52Updated last year
- ☆19Updated 2 years ago
- 交大電子所-積體電路實驗設計-李鎮宜教授☆12Updated 11 months ago
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆18Updated 2 years ago
- ☆28Updated 7 months ago
- ☆10Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆181Updated 2 years ago
- A collection of commonly asked RTL design interview questions☆31Updated 8 years ago
- NYCU ICLAB 2025 spring codes & 心得☆15Updated 3 weeks ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆158Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆53Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆42Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆39Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago