☆57Jul 2, 2023Updated 2 years ago
Alternatives and similar repositories for RISC-V_SoC
Users that are interested in RISC-V_SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆37Feb 10, 2025Updated last year
- SoC for muntjac☆13Jun 18, 2025Updated 11 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Jun 7, 2026Updated last week
- ☆16May 27, 2024Updated 2 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 題目練習☆13Sep 29, 2022Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- RISCV CPU implementation in SystemVerilog☆32Jun 7, 2026Updated last week
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆165Sep 9, 2024Updated last year
- IC Contest☆47Mar 28, 2023Updated 3 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- 楊家驤老師的"電腦輔助積體電路系統設計"作業(CVSD)☆44Oct 6, 2024Updated last year
- Professor: C.H. Yang☆10Aug 16, 2025Updated 9 months ago
- 64-bit multicore Linux-capable RISC-V processor☆114Apr 28, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Jul 28, 2022Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- NTHU CS6135 VLSI實體設計自動化☆12Mar 12, 2022Updated 4 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆25Mar 7, 2019Updated 7 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆15Mar 26, 2024Updated 2 years ago
- Basic LLVM passes☆17Oct 7, 2018Updated 7 years ago
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆18Apr 28, 2026Updated last month
- FPGA Labs for EECS 151/251A (Fall 2021)☆12Oct 20, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- 更優質的選課網站 | A new site for NCKU course enrollment☆45Feb 24, 2025Updated last year
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆26Jun 7, 2026Updated last week
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆39Jun 22, 2023Updated 2 years ago
- A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.☆24Oct 29, 2023Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- The official NaplesPU hardware code repository☆31Jul 27, 2019Updated 6 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- 💾 FreeRTOS port for the NEORV32 RISC-V Processor.☆15Jun 1, 2026Updated 2 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- NCTU OSDI 2020☆28Sep 3, 2020Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆19Feb 27, 2025Updated last year
- ☆13Oct 20, 2020Updated 5 years ago
- USB2.0 Device Controller IP Core☆16Aug 18, 2023Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆71Feb 13, 2025Updated last year
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21May 12, 2026Updated last month
- ☆14Aug 14, 2023Updated 2 years ago