Alternatives and similar repositories for RISC-V_SoC:

Users that are interested in RISC-V_SoC are comparing it to the libraries listed below

• eisl-nctu / aquila
  Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.
  ☆30Updated last year
• eisl-nctu / falco
  A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
  ☆16Updated 3 years ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆26Updated 2 years ago
• yutongshen / RISC-V-Emulator
  ☆29Updated last month
• yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynq
  Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
  ☆10Updated 3 months ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆197Updated last month
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆57Updated last week
• albertfan1120 / NTU_CVSD_2021
  Computer-Aided VLSI System Design
  ☆18Updated 5 months ago
• max2468tw / IC_Lab
  NCTU 2018 Spring Integrated Circuit Design Laboratory
  ☆24Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆139Updated 10 months ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• Ni-ChiTing / IC_contest_cell_based_design
  ☆11Updated 3 years ago
• bol-edu / caravel-soc
  ☆28Updated last year
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆35Updated 3 weeks ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆140Updated this week
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 7 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆55Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆129Updated 2 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated this week
• bol-edu / caravel-soc_fpga-lab
  ☆16Updated last week
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆138Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated last week
• zli87 / Integrated_Circuit_Design_Laboratory_IC_Lab
  Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
  ☆23Updated 3 years ago