yutongshen / RISC-V_SoCLinks
☆38Updated 2 years ago
Alternatives and similar repositories for RISC-V_SoC
Users that are interested in RISC-V_SoC are comparing it to the libraries listed below
Sorting:
- A simple superscalar out-of-order RISC-V microprocessor☆212Updated 5 months ago
- Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.☆32Updated last year
- Simple 3-stage pipeline RISC-V processor☆140Updated last week
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆56Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- PCI Express controller model☆60Updated 2 years ago
- 伴伴學 RISC-V RV32I Architecture CPU☆30Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆71Updated last month
- Learn systemC with examples☆118Updated 2 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆37Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 11 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Ariane is a 6-stage RISC-V CPU☆141Updated 5 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- RISC-V Verification Interface☆100Updated 2 months ago
- A libgloss replacement for RISC-V that supports HTIF☆38Updated last year
- ☆29Updated 5 years ago
- ☆63Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆105Updated 4 years ago
- Pure digital components of a UCIe controller☆66Updated 3 weeks ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- ☆52Updated 6 years ago
- QEMU libsystemctlm-soc co-simulation demos.☆152Updated 2 months ago
- ☆66Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- Vector processor for RISC-V vector ISA☆122Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- Wrapper for Rocket-Chip on FPGAs☆135Updated 2 years ago