☆47Jul 2, 2023Updated 2 years ago
Alternatives and similar repositories for RISC-V_SoC
Users that are interested in RISC-V_SoC are comparing it to the libraries listed below
Sorting:
- ☆35Feb 10, 2025Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- 題目練習☆13Sep 29, 2022Updated 3 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- ☆12Jul 28, 2022Updated 3 years ago
- ☆13May 27, 2024Updated last year
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆11Dec 26, 2024Updated last year
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆17Feb 2, 2026Updated last month
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- 楊家驤老師的"電腦輔助積體電路系統設計"作業(CVSD)☆42Oct 6, 2024Updated last year
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆14Jan 30, 2024Updated 2 years ago
- NCTU OSDI 2020☆28Sep 3, 2020Updated 5 years ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆156Sep 9, 2024Updated last year
- Basic LLVM passes☆17Oct 7, 2018Updated 7 years ago
- IC Contest☆44Mar 28, 2023Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- ☆10Jun 7, 2022Updated 3 years ago
- Qbox☆84Feb 25, 2026Updated last week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 4 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- ☆18Jul 5, 2023Updated 2 years ago
- A fork of Xiangshan for AI☆36Updated this week
- 深入淺出教你寫編譯器（Compiler）☆16Aug 29, 2019Updated 6 years ago
- 更優質的選課網站 | A new site for NCKU course enrollment☆44Feb 24, 2025Updated last year
- Simple 3-stage pipeline RISC-V processor☆146Feb 24, 2026Updated last week
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Mar 7, 2019Updated 6 years ago
- Verilog source code for book: Computer Architecture Tutorial☆26Oct 12, 2021Updated 4 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 3 months ago