☆59Jul 2, 2023Updated 3 years ago
Alternatives and similar repositories for RISC-V_SoC
Users that are interested in RISC-V_SoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆37Feb 10, 2025Updated last year
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆12Dec 26, 2024Updated last year
- SoC for muntjac☆14Jun 18, 2025Updated last year
- IC Contest☆47Mar 28, 2023Updated 3 years ago
- ☆14Aug 14, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Computer Architecture UIUC SP 2018☆15May 4, 2018Updated 8 years ago
- Intel(R) 8051 Instruction Set Simulator☆14Aug 17, 2023Updated 3 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- 題目練習☆13Sep 29, 2022Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- RISCV CPU implementation in SystemVerilog☆32Aug 28, 2026Updated last week
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- Professor: C.H. Yang☆10Aug 16, 2025Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆120Apr 28, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.☆23Updated this week
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- ☆16May 25, 2026Updated 3 months ago
- ☆18May 27, 2024Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆25Mar 7, 2019Updated 7 years ago
- Basic LLVM passes☆17Oct 7, 2018Updated 7 years ago
- Open Source T-series ISP driver☆18Updated this week
- FPGA Labs for EECS 151/251A (Fall 2021)☆13Oct 20, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An evolving Post-Quantum Cryptography (PQC) RISC-V extension architecture.☆17Jul 31, 2026Updated last month
- 楊家驤老師的"電腦輔助積體電路系統設計"作業(CVSD)☆50Oct 6, 2024Updated last year
- A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.☆24Oct 29, 2023Updated 2 years ago
- ☆39Jun 13, 2026Updated 2 months ago
- 32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss dat…☆15Aug 20, 2026Updated 2 weeks ago
- ☆13Oct 20, 2020Updated 5 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- USB2.0 Device Controller IP Core☆19Aug 18, 2023Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- NCTU OSDI 2020☆30Sep 3, 2020Updated 6 years ago
- 黃鐘揚老師的"系統晶片驗證"作業與專題(SoCV)☆11Jan 18, 2024Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆20Feb 27, 2025Updated last year
- 💾 FreeRTOS port for the NEORV32 RISC-V Processor.☆17Updated this week