Alternatives and similar repositories for xup_embedded_system_design_flow

Users that are interested in xup_embedded_system_design_flow are comparing it to the libraries listed below

• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆85Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• oprecomp / DDR4_controller
  ☆69Updated 4 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆78Updated 11 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆119Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated last week
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆180Updated 2 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆76Updated 6 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆42Updated 2 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆135Updated 7 years ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆33Updated 3 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆97Updated 3 weeks ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆82Updated 2 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆99Updated 4 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆70Updated 5 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆83Updated 7 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆95Updated 6 years ago
• tms4517 / 2D-Systolic-Array-Multiplier
  2D Systolic Array Multiplier
  ☆22Updated last year
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆54Updated 4 years ago
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆54Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• opensmartnic / cocotb_primer
  understanding of cocotb （In Chinese Only）
  ☆20Updated 5 months ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆68Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆181Updated last year