CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target
☆26May 12, 2025Updated last year
Alternatives and similar repositories for cmake-verilog-vhdl-fpga-template
Users that are interested in cmake-verilog-vhdl-fpga-template are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Doxygen with verilog support☆41Mar 15, 2019Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Gesture Recognition Based on ALTERA DE2-115 FPGA☆12Mar 18, 2014Updated 12 years ago
- This repository contains FPGA code for various projects like Lighthouse Tracking as well as some IP cores. The repository is board-indepe…☆14Sep 8, 2021Updated 4 years ago
- Reflection API for SystemVerilog☆14Mar 30, 2026Updated 4 months ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board.☆11May 2, 2013Updated 13 years ago
- PLL Simulator in SystemC-AMS☆11Jun 2, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VEXTPROJ - the version control friendly system for creation of Vivado projects☆13Oct 25, 2025Updated 9 months ago
- Photoshop Actions to mimic Instagram filters☆11Jan 3, 2017Updated 9 years ago
- This repository includes some FPGA projects like VGA control, image processing. So far, fpga can drive a VGA monitor and display an image…☆14Jul 5, 2017Updated 9 years ago
- SystemC Design of a Master/Slave I2C Bus☆18Aug 14, 2015Updated 10 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆17Jan 10, 2018Updated 8 years ago
- ChimeraTK core library: Provide (client) access to hardware devices and other control system applications.☆12Jul 27, 2026Updated 2 weeks ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆101May 24, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FreeRTOS port for the RISC-V Virtual Prototype☆14Nov 9, 2020Updated 5 years ago
- Binary to ROOT Tree Converter.☆11Nov 29, 2018Updated 7 years ago
- mvme - mesytec VME data acquisition☆11Updated this week
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆291Nov 25, 2019Updated 6 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- c++ disassembly library☆15May 22, 2017Updated 9 years ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An RS232 communication controller implemented in VHDL☆16Jun 23, 2026Updated last month
- Fork of the ski ia64 emulator☆13May 15, 2016Updated 10 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- A collection of VHDL projects for generating VGA output☆26Nov 26, 2018Updated 7 years ago
- Software for Bill Shen's Z280RC Single Board Z280 system on a RC2014 board☆16Jun 16, 2026Updated last month