Alternatives and similar repositories for Examples

Users that are interested in Examples are comparing it to the libraries listed below

• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆171Updated this week
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last month
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆152Updated last month
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆71Updated 2 weeks ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆101Updated last month
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆52Updated last year
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆59Updated 7 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆106Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆96Updated last year
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆72Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆55Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆143Updated 3 weeks ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• jamieiles / uart
  Verilog UART
  ☆172Updated 12 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated 2 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆151Updated 11 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆63Updated 2 weeks ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆137Updated 3 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆77Updated last year
• OSVVM / Documentation
  OSVVM Documentation
  ☆34Updated this week
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆133Updated 2 years ago
• HDLForBeginners / Toolbox
  ☆72Updated 10 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆135Updated 3 years ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆70Updated 3 years ago