☆122Sep 2, 2023Updated 2 years ago
Alternatives and similar repositories for Examples
Users that are interested in Examples are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Jul 14, 2021Updated 4 years ago
- A collection of Opal Kelly provided design resources☆17Nov 7, 2025Updated 4 months ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 7 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆79Apr 11, 2022Updated 3 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆39Feb 18, 2024Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆22Oct 8, 2021Updated 4 years ago
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 5 years ago
- ☆33Apr 30, 2023Updated 2 years ago
- An AMD/Xilinx Artix 50T FPGA on a Pi5 Hat with PCIe and GPIO interconnects as well as SPI programming☆17Sep 25, 2024Updated last year
- Ethernet interface modules for Cocotb☆76Sep 8, 2025Updated 6 months ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆13Jan 21, 2022Updated 4 years ago
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 6 years ago
- Triple Modular Redundancy☆30Sep 4, 2019Updated 6 years ago
- This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog☆31Nov 20, 2018Updated 7 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- Test dashboard for verification features in Verilator☆31Updated this week
- A C implementation of the Tsetlin Machine☆16Feb 6, 2026Updated last month
- ☆15Jan 9, 2022Updated 4 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Sep 16, 2020Updated 5 years ago
- Apio examples☆37Updated this week
- ☆14Feb 28, 2023Updated 3 years ago
- Collection of hardware description languages writings and code snippets☆28Jan 29, 2015Updated 11 years ago
- ☆13Feb 1, 2025Updated last year
- Programmable multichannel ADPCM decoder for FPGA☆25Dec 28, 2020Updated 5 years ago
- ☆16Mar 16, 2026Updated last week
- Study notes and tutorial for xilinx hls☆20Jul 22, 2021Updated 4 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆22Feb 16, 2022Updated 4 years ago
- ☆19Sep 14, 2025Updated 6 months ago
- DSP by FPGA☆15Sep 12, 2023Updated 2 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Feb 4, 2024Updated 2 years ago
- Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board☆12Sep 15, 2022Updated 3 years ago
- Nitro USB FPGA core☆86Mar 1, 2026Updated 3 weeks ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Mar 5, 2026Updated 2 weeks ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated last month
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- port of Stephen A. Edwards apple2fpga to ULX3S☆18Mar 27, 2024Updated last year
- LiteX-based gateware for LimeSDR boards.☆19Updated this week
- A collection for GNU radio blocks to implemenet guitar effects☆11Sep 12, 2018Updated 7 years ago