Alternatives and similar repositories for vpm

Users that are interested in vpm are comparing it to the libraries listed below

• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆182Updated this week
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆154Updated 3 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆155Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆206Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆90Updated 11 months ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆238Updated last month
• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆106Updated last month
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆115Updated 5 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆218Updated 8 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆442Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated 2 weeks ago
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆304Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆120Updated this week
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆170Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆306Updated 9 months ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆256Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 4 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆161Updated 2 weeks ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆126Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆142Updated 8 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆92Updated 5 months ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆319Updated 8 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated 3 weeks ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆114Updated this week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆220Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆124Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 2 months ago