Verilog package manager written in Rust
☆147Oct 5, 2024Updated last year
Alternatives and similar repositories for vpm
Users that are interested in vpm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated last year
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- Brilliantly Radical Artificially Intelligent Neural Machine☆18Dec 28, 2017Updated 8 years ago
- List of awesome semiconductor startups☆780Sep 2, 2026Updated last month
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆169Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A dependency management tool for hardware projects.☆393Sep 24, 2026Updated last week
- An abstraction library for interfacing EDA tools☆801Sep 15, 2026Updated 2 weeks ago
- A Python package for creating and solving constrained randomization problems.☆19Sep 24, 2026Updated last week
- An FPGA in your USB Port☆11Jul 1, 2021Updated 5 years ago
- Veryl: A Modern Hardware Description Language☆1,040Updated this week
- List of awesome open source hardware projects☆361Jan 2, 2023Updated 3 years ago
- An experimental package manager and development tool for Hardware Description Languages (HDL).☆14Apr 10, 2022Updated 4 years ago
- GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input …☆269Aug 20, 2024Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- An open-source HDL register code generator fast enough to run in real time.☆91Sep 24, 2026Updated last week
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 4 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- CRCat: Complex Rational Catalog of all Possible RLC Networks of up to and Including Five Elements☆35Nov 22, 2025Updated 10 months ago
- Bazel build rules for compiling Verilog☆22Mar 4, 2024Updated 2 years ago
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- The UVM written in Python☆570Updated this week
- Code generation tool for control and status registers☆471Sep 11, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Digital Design Equivalence Checking☆110Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,468Sep 25, 2026Updated last week
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆44Aug 25, 2026Updated last month
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Fully opensource spiking neural network accelerator☆179Feb 13, 2023Updated 3 years ago
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated 2 weeks ago
- ABACUS is a tool for approximate logic synthesis☆14Jul 13, 2020Updated 6 years ago
- WAL enables programmable waveform analysis.☆185Sep 22, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Universal Memory Interface (UMI)☆169Updated this week
- Common SystemVerilog components☆806Sep 18, 2026Updated 2 weeks ago
- Convert Verilog to a Hardcaml design☆23Jul 10, 2026Updated 2 months ago
- Slides of Dr Sparsh Mittal on "Computer Architecture for AI" (aka Hardware Architecture for Deep Learning) Course☆20Apr 20, 2026Updated 5 months ago
- cocotb: Python-based chip (RTL) verification☆2,530Updated this week
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆62Jul 25, 2026Updated 2 months ago
- Top level for the November shuttle☆13Nov 20, 2021Updated 4 years ago