getinstachip / vpm

Related projects ⓘ

Alternatives and complementary repositories for vpm

• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆142Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆65Updated this week
• google / sky90fd-pdk
  ☆107Updated last year
• asinghani / open-eda-course
  ☆52Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆108Updated this week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆138Updated 3 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆68Updated 11 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆81Updated 6 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆134Updated 5 months ago
• aignacio / nox
  RISC-V Nox core
  ☆61Updated 3 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆105Updated 2 months ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆70Updated last month
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆138Updated this week
• riscv-steel / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆158Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆169Updated this week
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆110Updated 2 weeks ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆53Updated 2 weeks ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆271Updated this week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆200Updated this week
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆139Updated 4 months ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆45Updated last month
• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆81Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆76Updated 2 months ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆211Updated this week
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆81Updated 6 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆73Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆52Updated last month
• efabless / chipignite-resources
  ☆76Updated 2 years ago