getinstachip / vpmLinks
Verilog package manager written in Rust
☆143Updated last year
Alternatives and similar repositories for vpm
Users that are interested in vpm are comparing it to the libraries listed below
Sorting:
- ASIC implementation flow infrastructure, successor to OpenLane☆268Updated this week
- Universal Memory Interface (UMI)☆157Updated this week
- Fabric generator and CAD tools.☆214Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆255Updated 4 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆200Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆132Updated this week
- Self checking RISC-V directed tests☆119Updated 7 months ago
- Communication framework for RTL simulation and emulation.☆308Updated 3 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 2 months ago
- Raptor end-to-end FPGA Compiler and GUI☆94Updated last year
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆265Updated 3 years ago
- A hardware component library developed with ROHD.☆111Updated last week
- SystemVerilog synthesis tool☆225Updated 10 months ago
- ☆47Updated 2 years ago
- SystemVerilog frontend for Yosys☆191Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆245Updated 4 months ago
- ☆122Updated 2 years ago
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- The multi-core cluster of a PULP system.☆111Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆97Updated 7 months ago
- A Python package to use FPGA development tools programmatically.☆143Updated 10 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 3 months ago
- An overview of TL-Verilog resources and projects☆82Updated last month
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆329Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆73Updated 3 years ago
- Waveform Viewer Extension for VScode☆307Updated this week