andrewbartolo / accel-sim
Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing
☆7Updated 5 years ago
Related projects: ⓘ
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 4 years ago
- ☆13Updated 4 years ago
- ☆31Updated 3 years ago
- ☆27Updated 5 years ago
- ☆17Updated last year
- Fibertree emulator☆11Updated last month
- Learn NVDLA by SOMNIA☆26Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 3 weeks ago
- ☆10Updated 10 months ago
- An implementation of a BinaryConnect network for cifar10☆11Updated 4 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆22Updated 4 months ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆12Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆26Updated last year
- ☆13Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆20Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆23Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆55Updated last month
- ☆15Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆26Updated 2 years ago
- ☆20Updated last year
- ☆21Updated 5 months ago
- A high-level performance analysis tool for FPGA-based accelerators☆18Updated 7 years ago
- Documentation for the entire CGRAFlow☆17Updated 3 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆31Updated 11 months ago
- ☆17Updated 6 years ago
- ☆15Updated 4 years ago
- ☆32Updated 5 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago