Alternatives and similar repositories for accel-sim:

Users that are interested in accel-sim are comparing it to the libraries listed below

• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 weeks ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• priyanka-raina / dnn-accelerator
  ☆13Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• maestro-project / gamma-timeloop
  ☆14Updated last year
• fpga-opencl-benchmarks / rodinia_fpga
  Rodinia Benchmark Suite for OpenCL-based FPGAs
  ☆31Updated last year
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• IronySuzumiya / NiuDianNao
  A simple cycle-accurate DaDianNao simulator
  ☆13Updated 5 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 6 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆63Updated 3 years ago
• Accelergy-Project / processing-in-memory-design
  ☆26Updated 10 months ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆33Updated 5 years ago
• Fibertree-Project / fibertree
  Fibertree emulator
  ☆12Updated 4 months ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆23Updated 3 months ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆19Updated 7 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆18Updated 6 years ago
• UCLA-VAST / soda
  Stencil with Optimized Dataflow Architecture
  ☆15Updated last year
• union-codesign / union
  ☆15Updated 3 years ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆18Updated 10 months ago
• suchandler96 / gem5-NVDLA
  ☆29Updated 5 months ago
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 3 years ago