andrewbartolo / accel-simLinks
Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing
☆7Updated 6 years ago
Alternatives and similar repositories for accel-sim
Users that are interested in accel-sim are comparing it to the libraries listed below
Sorting:
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- ☆35Updated 4 years ago
- ☆29Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- ☆25Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆13Updated 4 years ago
- ☆15Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- Fibertree emulator☆12Updated 7 months ago
- ☆33Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 6 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆53Updated 2 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- ☆19Updated 5 years ago
- research, experimentation and implementation of hardware-agnostic accelerated DL framework☆36Updated 3 weeks ago
- ☆14Updated 3 years ago
- ☆12Updated 3 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- Jumpstart your custom DNN accelerator today. This project holds scripts to build and start containers that can compile binaries to the ze…☆10Updated 5 years ago
- ☆16Updated 7 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 9 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago