andre1araujo / YOLO-on-PYNQ-Z2
This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.
☆32Updated last week
Related projects ⓘ
Alternatives and complementary repositories for YOLO-on-PYNQ-Z2
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- An AIoT project based on PYNQ-Z2 FPGA Evaluation board. Reading image from usb camera and running yolov3-tiny detection with DPU and usin…☆10Updated 2 years ago
- Zynq-7000 DPU TRD☆43Updated 5 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆67Updated last year
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆37Updated 7 months ago
- hls code zynq 7020 pynq z2 CNN☆77Updated 5 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆70Updated 3 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆34Updated 4 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆89Updated 11 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆121Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆127Updated 5 months ago
- FPGA/AES/LeNet/VGG16☆88Updated 6 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆26Updated 2 years ago
- ☆45Updated last year
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆21Updated 3 years ago
- Pynq computer vision examples with an OV5640 camera☆46Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆160Updated 8 months ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆66Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- FPGA实现动态图像识别☆13Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆61Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆29Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆167Updated last year
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆35Updated 4 years ago
- ☆43Updated 6 years ago