andre1araujo / YOLO-on-PYNQ-Z2Links
This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.
☆97Updated 9 months ago
Alternatives and similar repositories for YOLO-on-PYNQ-Z2
Users that are interested in YOLO-on-PYNQ-Z2 are comparing it to the libraries listed below
Sorting:
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建 议添加外部存储及DDR☆138Updated 2 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆67Updated last year
- Implement Tiny YOLO v3 on ZYNQ☆310Updated 8 months ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆261Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆175Updated 2 years ago
- ☆56Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆191Updated last year
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆84Updated 9 months ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬 件(xilinx fpga)加速的代码☆87Updated 3 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆85Updated 4 years ago
- some interesting demos for starters☆93Updated 3 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆19Updated last year
- 一个开源的FPGA神经网络加速器。☆185Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆219Updated last year
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆30Updated 3 years ago
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- FPGA☆159Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆217Updated 2 months ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆237Updated 2 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆163Updated 5 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- FPGA实现动态图像识别☆23Updated 5 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆37Updated last year
- Low-Precision YOLO on PYNQ with FINN☆34Updated 2 years ago
- 可运行☆38Updated 3 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆104Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago