sumilao / Zynq-7000-DPU-TRDLinks
Zynq-7000 DPU TRD
☆47Updated 6 years ago
Alternatives and similar repositories for Zynq-7000-DPU-TRD
Users that are interested in Zynq-7000-DPU-TRD are comparing it to the libraries listed below
Sorting:
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆64Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆72Updated 7 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆168Updated 2 years ago
- DPU on PYNQ☆237Updated 5 months ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆49Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆157Updated last year
- A DNN Accelerator implemented with RTL.☆68Updated last year
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- IC implementation of TPU☆144Updated 6 years ago
- ☆48Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆61Updated 3 years ago
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- An LeNet RTL implement onto FPGA☆51Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- Tutorials on Vitis AI Created by LogicTronix!☆34Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆160Updated 10 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆240Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 5 years ago
- PYNQ Composabe Overlays☆74Updated last year
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆74Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago