sumilao / Zynq-7000-DPU-TRD
Zynq-7000 DPU TRD
☆44Updated 5 years ago
Alternatives and similar repositories for Zynq-7000-DPU-TRD:
Users that are interested in Zynq-7000-DPU-TRD are comparing it to the libraries listed below
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- ☆43Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆45Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 weeks ago
- ☆60Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆22Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- ☆99Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆68Updated 6 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆73Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆175Updated last year
- The second place winner for DAC-SDC 2020☆96Updated 2 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆27Updated 2 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆36Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- ☆39Updated 5 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆47Updated 5 years ago