Alternatives and similar repositories for single-cycle-cpu

Users that are interested in single-cycle-cpu are comparing it to the libraries listed below

• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆107Updated 3 months ago
• TinyTapeout / tt07-verilog-template
  Submission template for Tiny Tapeout 7 - Verilog HDL Projects
  ☆21Updated last year
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆90Updated 11 months ago
• TinyTapeout / tt10-verilog-template
  Submission template for Tiny Tapeout 10 - Verilog HDL Projects
  ☆25Updated 5 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• erinadreno / list_of_Xilinx_FPGAs
  ☆38Updated 4 months ago
• TinyTapeout / tt06-verilog-template
  Submission template for Tiny Tapeout 6 - Verilog HDL Projects
  ☆34Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 2 weeks ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆154Updated this week
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated last month
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last month
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 5 years ago
• TinyTapeout / ttihp-verilog-template
  Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects
  ☆22Updated 7 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆117Updated last year
• EECS150 / asic-labs-fa22
  ☆20Updated 2 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆70Updated this week
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆18Updated 4 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated 2 weeks ago
• tinyvision-ai-inc / Hands-on-FPGA-class
  ☆52Updated 3 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 6 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆167Updated this week
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated this week
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆167Updated 4 years ago