Alternatives and similar repositories for single-cycle-cpu

Users that are interested in single-cycle-cpu are comparing it to the libraries listed below

• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• TinyTapeout / tt07-verilog-template
  Submission template for Tiny Tapeout 7 - Verilog HDL Projects
  ☆21Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆106Updated 2 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• TinyTapeout / tt10-verilog-template
  Submission template for Tiny Tapeout 10 - Verilog HDL Projects
  ☆25Updated 4 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆60Updated last year
• dkilfoyle / logic2
  Digital Logic Simulator
  ☆34Updated 4 years ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆66Updated 6 years ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆153Updated last week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated 3 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆122Updated 3 months ago
• jogeshsingh / Learning-about-FPGA-DESIGN-
  This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …
  ☆38Updated 7 months ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆163Updated 4 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated 2 weeks ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 2 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 5 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆70Updated last week
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆186Updated 3 weeks ago
• dpretet / friscv
  RISCV CPU implementation in SystemVerilog
  ☆32Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆86Updated 10 months ago
• nandland / getting-started-with-fpgas
  Verilog and VHDL for book
  ☆113Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• TinyTapeout / ttihp-verilog-template
  Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects
  ☆21Updated 6 months ago
• TimRudy / uart-verilog
  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
  ☆35Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆162Updated 2 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last week
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆65Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆132Updated 3 weeks ago