openXC7 / toolchain-nix
Nix flake for openXC7
☆31Updated 3 months ago
Alternatives and similar repositories for toolchain-nix:
Users that are interested in toolchain-nix are comparing it to the libraries listed below
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆54Updated this week
- Demo projects for various Kintex FPGA boards☆50Updated 8 months ago
- Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…☆44Updated this week
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 7 months ago
- PicoRV☆44Updated 5 years ago
- ☆44Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆41Updated this week
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- Board definitions for Amaranth HDL☆108Updated 2 weeks ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆87Updated 5 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆65Updated 8 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆35Updated 2 months ago
- System on Chip toolkit for Amaranth HDL☆86Updated 4 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Use ECP5 JTAG port to interact with user design☆26Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated this week
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆95Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆94Updated 7 months ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆42Updated last month
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 9 months ago
- 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).☆21Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆28Updated last year
- Tiny tips for Colorlight i5 FPGA board☆56Updated 3 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week