TimRudy / uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
☆29Updated last year
Alternatives and similar repositories for uart-verilog:
Users that are interested in uart-verilog are comparing it to the libraries listed below
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 11 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆68Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆128Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Wishbone interconnect utilities☆39Updated 2 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆85Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- Pipelined RISC-V RV32I Core in Verilog☆38Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated this week
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆47Updated 2 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- Minimal DVI / HDMI Framebuffer☆80Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆30Updated 2 years ago
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆45Updated 10 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆61Updated last week
- UART -> AXI Bridge☆61Updated 3 years ago
- ☆131Updated 4 months ago
- Many peripherals in Verilog ready to use☆36Updated 3 months ago
- Two Level Cache Controller implementation in Verilog HDL☆42Updated 4 years ago
- Tools for FPGA development.☆44Updated last year
- RISC-V Nox core☆62Updated last month
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- Open source ISS and logic RISC-V 32 bit project☆50Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆21Updated 6 years ago