TimRudy / uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
☆20Updated last year
Related projects ⓘ
Alternatives and complementary repositories for uart-verilog
- Wishbone interconnect utilities☆37Updated 5 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated last year
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Tools for FPGA development.☆44Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 7 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆25Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆23Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆48Updated last week
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆48Updated last year
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆45Updated this week
- CologneChip GateMate FPGA Module: GMM-7550☆18Updated 9 months ago
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆46Updated 3 weeks ago
- Portable HyperRAM controller☆48Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆66Updated this week
- Small (Q)SPI flash memory programmer in Verilog☆55Updated 2 years ago
- Master-thesis-final☆18Updated last year
- SoftCPU/SoC engine-V☆54Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- ☆31Updated last week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- ☆57Updated 3 years ago