TimRudy / uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
☆28Updated last year
Alternatives and similar repositories for uart-verilog:
Users that are interested in uart-verilog are comparing it to the libraries listed below
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 11 months ago
- A simple implementation of a UART modem in Verilog.☆125Updated 3 years ago
- Wishbone interconnect utilities☆39Updated last month
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 2 weeks ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆61Updated this week
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆78Updated this week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆67Updated 2 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- Lecture about FIR filter on an FPGA☆11Updated 10 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Verilog wishbone components☆113Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Tools for FPGA development.☆44Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆84Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆68Updated 2 years ago
- Pipelined RISC-V RV32I Core in Verilog☆38Updated last year
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆21Updated 6 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆30Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆51Updated last year
- Verilog implementation of a RISC-V core☆110Updated 6 years ago
- RISC-V Nox core☆62Updated last week
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago