TinyTapeout / tt07-verilog-templateLinks
Submission template for Tiny Tapeout 7 - Verilog HDL Projects
☆19Updated last year
Alternatives and similar repositories for tt07-verilog-template
Users that are interested in tt07-verilog-template are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- Raptor end-to-end FPGA Compiler and GUI☆86Updated 10 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆77Updated this week
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 6 months ago
- tools used by project repos to test configuration, generate OpenLane run summaries and documentation☆26Updated last week
- SAR ADC on tiny tapeout☆42Updated 8 months ago
- Submission template for Tiny Tapeout 10 - Verilog HDL Projects☆25Updated 3 months ago
- Fabric generator and CAD tools graphical frontend☆16Updated 2 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆52Updated last year
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆61Updated last month
- A pipelined RISC-V processor☆62Updated last year
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆59Updated last month
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆55Updated 3 weeks ago
- Submission template for Tiny Tapeout 03☆20Updated 2 years ago
- Submission template for Tiny Tapeout 6 - Verilog HDL Projects☆34Updated last year
- Flip flop setup, hold & metastability explorer tool☆51Updated 2 years ago
- ☆38Updated 11 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- ☆70Updated last year
- End-to-End Open-Source I2C GPIO Expander☆33Updated 3 months ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Many peripherals in Verilog ready to use☆39Updated 9 months ago
- FPGA examples on Google Colab☆27Updated 2 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆83Updated this week
- Submission template for Tiny Tapeout 8 - Verilog HDL Projects☆18Updated last year
- A Risc-V SoC for Tiny Tapeout☆39Updated 2 weeks ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week