sifferman / fusesoc_templateLinks
Example of how to get started with olofk/fusesoc.
☆17Updated 4 years ago
Alternatives and similar repositories for fusesoc_template
Users that are interested in fusesoc_template are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- FPGA examples on Google Colab☆27Updated last month
- Demo projects for various Kintex FPGA boards☆62Updated 4 months ago
- Virtual Development Board☆62Updated 3 years ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 4 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆74Updated this week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆179Updated last year
- Drawio => VHDL and Verilog☆58Updated last year
- Flip flop setup, hold & metastability explorer tool☆50Updated 2 years ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆45Updated 2 years ago
- Projects published on controlpaths.com and hackster.io☆42Updated 3 years ago
- Documenting the Lattice ECP5 bit-stream format.☆55Updated 2 years ago
- Bitstream relocation and manipulation tool.☆46Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆96Updated this week
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 6 months ago
- VHDL PCIe Transceiver☆30Updated 5 years ago
- A series of CORDIC related projects☆115Updated 10 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆59Updated last month
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆90Updated 3 months ago
- Wishbone interconnect utilities☆42Updated 8 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆83Updated this week
- ☆106Updated 2 years ago
- A flexible and scalable development platform for modern FPGA projects.☆35Updated last month
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆110Updated last year
- SiliconCompiler Design Gallery☆51Updated this week
- Nitro USB FPGA core☆87Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆51Updated last year