sifferman / fusesoc_template
Example of how to get started with olofk/fusesoc.
☆17Updated 3 years ago
Alternatives and similar repositories for fusesoc_template:
Users that are interested in fusesoc_template are comparing it to the libraries listed below
- Demo projects for various Kintex FPGA boards☆53Updated 10 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆71Updated 10 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- ☆41Updated last year
- assorted library of utility cores for amaranth HDL☆87Updated 7 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆43Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆60Updated last week
- FPGA examples on Google Colab☆22Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆90Updated 7 months ago
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- End-to-End Open-Source I2C GPIO Expander☆31Updated last month
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 2 months ago
- Wishbone interconnect utilities☆39Updated 2 months ago
- A pipelined RISC-V processor☆55Updated last year
- Virtual Development Board☆59Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆56Updated 4 years ago
- Tools for FPGA development.☆44Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 3 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆44Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Drawio => VHDL and Verilog☆54Updated last year
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- SAR ADC on tiny tapeout☆38Updated 2 months ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆28Updated last year