otto-tom / can_axi4lite
CAN-bus Controller with AXI4-lite Interface
☆17Updated 3 weeks ago
Alternatives and similar repositories for can_axi4lite:
Users that are interested in can_axi4lite are comparing it to the libraries listed below
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- MIPI CSI-2 RX☆30Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆28Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆28Updated 9 months ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆33Updated last year
- JESD204b modules in VHDL☆29Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Verilog digital signal processing components☆125Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆47Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆22Updated 2 years ago
- Must-have verilog systemverilog modules☆30Updated 2 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- ☆53Updated 2 years ago
- An CAN bus Controller implemented in Verilog☆44Updated 9 years ago
- Verilog SPI master and slave☆48Updated 9 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated 2 months ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- SDRAM controller for MIPSfpga+ system☆21Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- ☆20Updated 5 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- I2C controller core☆37Updated 2 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆121Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆13Updated 2 years ago