Alternatives and similar repositories for KC705-AD9371:

Users that are interested in KC705-AD9371 are comparing it to the libraries listed below

• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• ymz000 / Kintex-7-xc7k325-pcb
  基于Kintex-7 XC7K325T的高性能FPGA功能验证板
  ☆19Updated 5 years ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆27Updated 5 months ago
• MicroPhase / antsdr_standalone
  Standalone application based on ADI hdl and no_OS for ANTSDR.
  ☆21Updated last year
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆12Updated this week
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 6 years ago
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆53Updated last month
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆25Updated 3 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆22Updated 6 years ago
• coltonshane / WAVE-Vivado
  HDL and C source for WAVE Zynq Ultrascale+ SoC
  ☆17Updated 3 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆20Updated 3 weeks ago
• VideoGPU / FMC_MIPI
  FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface
  ☆16Updated last year
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• FDU-ME-ARC / NVMeCHA
  ☆14Updated 3 years ago
• mwrnd / innova2_xcku15p_ddr4_bram_gpio
  XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
  ☆17Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated 2 months ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆27Updated last month
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated last year
• myriadrf / LimeSDR-PCIe_GW
  Altera Cyclone IV FPGA project for the PCIe LimeSDR board
  ☆38Updated 2 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆30Updated last year
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• ApotheoTech / Aper-Oculus
  An open-source Xilinx Kria SOM Carrier for high-speed camera design
  ☆22Updated last year
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆43Updated 3 years ago
• coole198669 / viterbi_decoder
  Hardware Viterbi Decoder in verilog
  ☆24Updated 5 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆46Updated last year
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆20Updated 4 years ago