The implementation of AD9371 on KC705
☆20Jun 10, 2025Updated 10 months ago
Alternatives and similar repositories for KC705-AD9371
Users that are interested in KC705-AD9371 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆21Apr 12, 2023Updated 3 years ago
- 文档编写☆13Sep 19, 2020Updated 5 years ago
- RF power detector board design files☆20Oct 25, 2016Updated 9 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- DDS board using the 1GSPS AD9910.☆18Dec 11, 2018Updated 7 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 5 years ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆31Dec 25, 2023Updated 2 years ago
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 7 years ago
- FPGA Technology Exchange Group相关文件管理☆68Jan 3, 2026Updated 4 months ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 months ago
- DDS AD9959驱动程序及硬件设计文件☆11Feb 27, 2020Updated 6 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32May 15, 2023Updated 2 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 3 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- This is the Analog Devices Inc. Yocto/OpenEmbedded layer☆52Oct 29, 2025Updated 6 months ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- FPGAandLAN☆28Jun 13, 2021Updated 4 years ago
- Zynq-Feather brings the power of a Xilinx Zynq SoC (ARM + FPGA) into the compact Adafruit Feather form factor — enabling modular, high-pe…☆49Apr 16, 2021Updated 5 years ago
- kernel port for juicevm☆13May 25, 2021Updated 4 years ago
- A module for TBT3☆44Dec 31, 2023Updated 2 years ago
- A USRP B200 compatible GPSDO board with the u-blox LEA-M8F☆16Jun 16, 2016Updated 9 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- zynqmp_cam_isp_demo linux软件项目☆23Dec 18, 2022Updated 3 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- An attempt to synthesize GPS signals in FPGA logic.☆20Feb 17, 2026Updated 2 months ago
- LiteX LUNA USB stack integration☆14Jun 12, 2022Updated 3 years ago
- 基于高云FPGA与AD9363/AD9361射频收发器,构建了一套灵活可重构的软件无线电(SDR)系统,通信核心代码纯Verilog实现。软硬件全开源,高速基带处理部署于FPGA,交互业务部署于Python上位机,通过千兆以太网交互,实现了QPSK等多种实时通信与动态参数配…☆79Apr 1, 2026Updated last month
- 360nosc0pe Yocto build environment☆12Aug 27, 2018Updated 7 years ago
- artix-7 PCIe dev board☆32Sep 27, 2017Updated 8 years ago