Alternatives and similar repositories for Dadda-Multiplier-using-CSA:

Users that are interested in Dadda-Multiplier-using-CSA are comparing it to the libraries listed below

• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• kuladeepsaireddy / OpenNoc
  ☆29Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆71Updated 7 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆60Updated 8 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆40Updated 2 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆31Updated 2 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 6 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆88Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 6 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆32Updated 2 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆24Updated 7 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• pulp-platform / fpu
  ☆41Updated 6 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆39Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 6 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆11Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆36Updated 2 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆131Updated 2 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆30Updated 2 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆39Updated 6 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆80Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆66Updated last year
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago