Alternatives and similar repositories for fcuda

Users that are interested in fcuda are comparing it to the libraries listed below

• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated 3 months ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆100Updated 2 years ago
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆91Updated last month
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆123Updated last year
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆78Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆55Updated 4 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆164Updated last year
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆120Updated 11 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆108Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆153Updated last year
• KastnerRG / spector
  Spector: An OpenCL FPGA Benchmark Suite
  ☆48Updated 6 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆87Updated 2 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆86Updated 2 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆69Updated 5 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆41Updated last year
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆110Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 7 months ago