This store contains Configurable Example Designs.
☆51Updated this week
Alternatives and similar repositories for XilinxCEDStore
Users that are interested in XilinxCEDStore are comparing it to the libraries listed below
Sorting:
- ☆315Updated this week
- ☆12Oct 8, 2020Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Jun 18, 2020Updated 5 years ago
- Xilinx Embedded Software (embeddedsw) Development☆13Updated this week
- An RFSoC Frequency Planner developed using Python.☆32May 22, 2023Updated 2 years ago
- Set of scripts for managing Vitis workspaces with git.☆15Dec 17, 2025Updated 2 months ago
- A repository of information and source files for toolflow-supported hardware☆32Jul 15, 2022Updated 3 years ago
- ☆14Jan 22, 2026Updated last month
- ☆15Mar 22, 2021Updated 4 years ago
- ☆23Apr 29, 2021Updated 4 years ago
- ☆16Oct 11, 2022Updated 3 years ago
- Vitis_Accel_Examples☆584Dec 17, 2025Updated 2 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- ☆70Jul 24, 2025Updated 7 months ago
- ☆26Updated this week
- Repo Manifests for the Yocto Project Build System☆40Jan 20, 2026Updated last month
- SLAC Python Based Hardware Abstraction & Data Acquisition System☆48Updated this week
- ☆22Jul 20, 2023Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated this week
- ☆27Jun 12, 2022Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆34Jun 22, 2023Updated 2 years ago
- few python scripts to clone all IP cores from opencores.org☆26Jan 8, 2024Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆26Nov 21, 2024Updated last year
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 3 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆56Feb 26, 2021Updated 5 years ago
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆267Nov 13, 2025Updated 3 months ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆182Aug 16, 2025Updated 6 months ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆82Jan 21, 2026Updated last month
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆115Apr 9, 2025Updated 10 months ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆879Jan 16, 2026Updated last month
- Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.☆66Nov 20, 2025Updated 3 months ago
- ☆13Mar 2, 2023Updated 2 years ago
- Vstream - Video Analytics pipeline with Hardware based accelerations (dev - stage)☆10Feb 2, 2024Updated 2 years ago
- This project aims at designing an easy self-made ultrasound imaging device. It mainly consists of "Phased-array transducer", "Pulse-contr…☆14Jun 28, 2023Updated 2 years ago
- Python productivity for RFSoC platforms☆89Oct 31, 2025Updated 4 months ago
- PYNQ Composabe Overlays☆75Jun 17, 2024Updated last year
- ☆117Jul 15, 2021Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Dec 16, 2021Updated 4 years ago