Alternatives and similar repositories for vivado-boards

Users that are interested in vivado-boards are comparing it to the libraries listed below

• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆643Updated last year
• Digilent / vivado-library
  ☆666Updated last month
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆246Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆631Updated 9 months ago
• Xilinx / XilinxBoardStore
  ☆312Updated last week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆423Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆450Updated this week
• alexforencich / verilog-uart
  Verilog UART
  ☆532Updated 11 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆566Updated 3 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆476Updated 2 months ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆600Updated 6 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆369Updated last month
• Xilinx / Vivado-Design-Tutorials
  ☆248Updated this week
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆601Updated 2 weeks ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆355Updated 8 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆555Updated 4 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆414Updated 4 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆679Updated 11 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆284Updated 5 years ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆687Updated last month
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆613Updated 7 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆456Updated 8 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆704Updated last month
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆713Updated 2 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆858Updated 11 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆536Updated last year
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆870Updated 4 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆285Updated last year
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆322Updated 2 years ago