Alternatives and similar repositories for vivado-boards

Users that are interested in vivado-boards are comparing it to the libraries listed below

• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆595Updated 8 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• Xilinx / XilinxBoardStore
  ☆290Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 3 months ago
• Digilent / vivado-library
  ☆621Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆440Updated last month
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆503Updated 2 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆494Updated 4 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆210Updated 3 weeks ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆361Updated this week
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆336Updated 8 years ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆581Updated 4 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆306Updated last year
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆296Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆492Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆354Updated last year
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆431Updated last month
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆818Updated 4 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆283Updated 3 weeks ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆671Updated 2 weeks ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆277Updated 5 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆625Updated 4 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆625Updated 3 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• Xilinx / PYNQ_Workshop
  ☆434Updated 10 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆409Updated 6 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆812Updated 4 months ago