Alternatives and similar repositories for vivado-boards

Users that are interested in vivado-boards are comparing it to the libraries listed below

• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆604Updated 8 months ago
• Digilent / vivado-library
  ☆627Updated last week
• Xilinx / XilinxBoardStore
  ☆291Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• alexforencich / verilog-uart
  Verilog UART
  ☆497Updated 5 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆509Updated 2 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆393Updated last week
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆364Updated 2 weeks ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆445Updated last month
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆635Updated 5 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆215Updated last month
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆357Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆328Updated last month
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆823Updated 4 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆307Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆497Updated 3 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆337Updated 8 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆297Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆272Updated 5 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆817Updated 5 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆628Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆258Updated 6 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆584Updated 4 years ago
• Xilinx / PYNQ_Workshop
  ☆438Updated 10 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆661Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆276Updated last year