Alternatives and similar repositories for Arty

Users that are interested in Arty are comparing it to the libraries listed below

• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆132Updated last year
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆83Updated last year
• FPGAwars / FPGA-peripherals
  Collection of open-source peripherals in Verilog
  ☆181Updated 3 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆184Updated 8 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆149Updated 3 years ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆138Updated 4 years ago
• ldoolitt / vhd2vl
  ☆136Updated 9 months ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 7 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• mcmayer / iCE40
  Lattice iCE40 FPGA experiments - Work in progress
  ☆105Updated 4 years ago
• jakubcabal / uart-for-fpga
  Simple UART controller for FPGA written in VHDL
  ☆102Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• WillGreen / timetoexplore
  Source code to accompany https://timetoexplore.net
  ☆63Updated 5 years ago
• nullobject / sdram-fpga
  A FPGA core for a simple SDRAM controller.
  ☆122Updated 3 years ago
• Future-Electronics-Design-Center / Creative-Eval-Board
  Future Electronics Creative Eval Board featuring a Microsemi SmartFusion2 or IGLOO2 FPGA
  ☆16Updated 5 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• open-tool-forge / summon-fpga-tools
  A simple script to build open-source FPGA tools.
  ☆53Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆81Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆123Updated 9 years ago
• matt-kimball / toygpu
  A simple GPU on a TinyFPGA BX
  ☆81Updated 7 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• hamsternz / FPGA_GigabitTx
  Sending UDP packets out over a Gigabit PHY with an FPGA.
  ☆42Updated 9 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated last month