Digilent / Arty-A7Links
☆15Updated last month
Alternatives and similar repositories for Arty-A7
Users that are interested in Arty-A7 are comparing it to the libraries listed below
Sorting:
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 7 years ago
- ☆98Updated last year
- A series of CORDIC related projects☆110Updated 8 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A collection of phase locked loop (PLL) related projects☆107Updated last year
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆85Updated 2 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆36Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 5 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- Verilog digital signal processing components☆146Updated 2 years ago
- Verilog wishbone components☆117Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆72Updated last month
- A collection of demonstration digital filters☆154Updated last year
- Verilog modules required to get the OV7670 camera working☆72Updated 7 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆63Updated 3 weeks ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 2 months ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆116Updated 4 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Single Port RAM, Dual Port RAM, FIFO☆26Updated 3 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆38Updated last year
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆64Updated 3 years ago
- ☆45Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- Drawio => VHDL and Verilog☆56Updated last year
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago
- I2C Master Verilog module☆35Updated 2 months ago