Digilent / Arty-A7Links
☆15Updated 2 months ago
Alternatives and similar repositories for Arty-A7
Users that are interested in Arty-A7 are comparing it to the libraries listed below
Sorting:
- A series of CORDIC related projects☆115Updated 10 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- A collection of phase locked loop (PLL) related projects☆111Updated last year
- Slides and lab instructions for the mastering MicroBlaze session☆36Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆90Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- ☆106Updated 2 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 7 months ago
- A collection of demonstration digital filters☆156Updated last year
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆74Updated 3 years ago
- Verilog digital signal processing components☆156Updated 2 years ago
- ☆39Updated 4 years ago
- Verilog wishbone components☆118Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆73Updated 3 weeks ago
- SDRAM controller for MIPSfpga+ system☆24Updated 4 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆39Updated 2 weeks ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆29Updated 8 months ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 8 months ago
- Verilog modules required to get the OV7670 camera working☆74Updated 7 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A compact, configurable RISC-V core☆12Updated 2 months ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Drawio => VHDL and Verilog☆57Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆66Updated 4 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆67Updated 3 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago