projf / display_controllerLinks
FPGA display controller with support for VGA, DVI, and HDMI.
☆230Updated 5 years ago
Alternatives and similar repositories for display_controller
Users that are interested in display_controller are comparing it to the libraries listed below
Sorting:
- A full-speed device-side USB peripheral core written in Verilog.☆232Updated 2 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆250Updated 6 years ago
- Opensource DDR3 Controller☆347Updated last week
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆239Updated 6 years ago
- Verilog digital signal processing components☆143Updated 2 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆294Updated last month
- WISHBONE SD Card Controller IP Core☆124Updated 2 years ago
- A simple, basic, formally verified UART controller☆304Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆475Updated 3 years ago
- A Video display simulator☆170Updated last month
- A simple implementation of a UART modem in Verilog.☆137Updated 3 years ago
- FPGA Logic Analyzer and GUI☆133Updated 2 years ago
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆279Updated 4 years ago
- Verilog UART☆171Updated 12 years ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆272Updated last year
- USB3 PIPE interface for Xilinx 7-Series☆216Updated 3 years ago
- Example LED blinking project for your FPGA dev board of choice☆177Updated 3 weeks ago
- High throughput JPEG decoder in Verilog for FPGA☆233Updated 3 years ago
- ☆133Updated 6 months ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- Verilog wishbone components☆115Updated last year
- Small footprint and configurable DRAM core☆418Updated 3 weeks ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆118Updated 4 years ago
- USB Serial on the TinyFPGA BX☆136Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- Fully parametrizable combinatorial parallel LFSR/CRC module☆149Updated 3 months ago
- FuseSoC standard core library☆143Updated 3 weeks ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆264Updated this week
- Bus bridges and other odds and ends☆568Updated 2 months ago
- ☆94Updated last year