projf / display_controller
FPGA display controller with support for VGA, DVI, and HDMI.
☆219Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for display_controller
- A Verilog implementation of DisplayPort protocol for FPGAs☆234Updated 5 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆215Updated 2 years ago
- Opensource DDR3 Controller☆217Updated this week
- WISHBONE SD Card Controller IP Core☆118Updated 2 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆211Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆371Updated 3 years ago
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆230Updated 5 years ago
- A simple, basic, formally verified UART controller☆282Updated 9 months ago
- Verilog digital signal processing components☆108Updated 2 years ago
- Verilog wishbone components☆109Updated 10 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago
- Verilog SDRAM memory controller☆311Updated 7 years ago
- Minimal DVI / HDMI Framebuffer☆76Updated 4 years ago
- High throughput JPEG decoder in Verilog for FPGA☆212Updated 2 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆259Updated 4 years ago
- Bus bridges and other odds and ends☆491Updated 10 months ago
- ☆121Updated last year
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆269Updated 4 years ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆251Updated 9 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- A simple RISC-V processor for use in FPGA designs.☆263Updated 3 months ago
- Example LED blinking project for your FPGA dev board of choice☆165Updated this week
- FPGA Logic Analyzer and GUI☆91Updated last year
- A Video display simulator☆156Updated 4 months ago
- USB3 PIPE interface for Xilinx 7-Series☆201Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆71Updated 7 months ago
- ☆78Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆87Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆266Updated 6 months ago