Digilent / embeddedsw

Related projects ⓘ

Alternatives and complementary repositories for embeddedsw

• Digilent / Arty-A7
  ☆16Updated 4 months ago
• Digilent / Genesys-ZU
  ☆10Updated 4 months ago
• Digilent / digilent-apps
  ☆14Updated last year
• freecores / uart16550
  UART 16550 core
  ☆30Updated 10 years ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆25Updated 2 weeks ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆26Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆11Updated 6 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆15Updated 4 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆28Updated 8 years ago
• Digilent / Arty-A7-35-XADC
  ☆18Updated 4 years ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆17Updated 5 years ago
• Goshik92 / FFTVisualizer
  This project demonstrates DSP capabilities of Terasic DE2-115
  ☆27Updated 6 years ago
• Digilent / u-boot-digilent
  u-boot-xarm from xilinx git repo with Digilent additions
  ☆31Updated 3 months ago
• freecores / pci
  PCI bridge
  ☆16Updated 10 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆12Updated 2 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆41Updated 2 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 10 years ago
• Digilent / digilent-vivado-scripts
  ☆63Updated 4 months ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆55Updated 2 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• suoto / fpga_cores
  ☆32Updated last year
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆40Updated last year
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆19Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago