Alternatives and similar repositories for tinycpu:

Users that are interested in tinycpu are comparing it to the libraries listed below

• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆82Updated last year
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆20Updated 7 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• gundy / tinyfpga-bx-game-soc
  A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
  ☆22Updated 6 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• olofk / i2c
  I2C controller core
  ☆16Updated 2 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• vsergeev / v8cpu
  v8cpu is a simple multi-cycle von Neumann architecture 8-bit CPU in under 500 lines of Verilog.
  ☆13Updated 7 years ago
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆35Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆18Updated 12 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆26Updated 4 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆62Updated 7 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆30Updated 4 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆47Updated 4 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated this week
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆54Updated this week
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 3 weeks ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 11 months ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆38Updated 7 years ago