fallen / tinycpu

Related projects ⓘ

Alternatives and complementary repositories for tinycpu

• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆80Updated 11 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆122Updated 10 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 2 weeks ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆85Updated 2 months ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆36Updated 6 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆19Updated 7 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 8 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆62Updated 4 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated 3 weeks ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆47Updated 3 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 5 years ago
• sdasgup3 / parallel-processor-design
  Super scalar Processor design
  ☆21Updated 10 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆116Updated last year
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆72Updated 5 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• jck / riscv
  ☆20Updated 11 months ago
• aliyun / alibabacloud-fpga
  ☆17Updated 5 years ago