Alternatives and similar repositories for tinycpu:

Users that are interested in tinycpu are comparing it to the libraries listed below

• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆81Updated last year
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆88Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆89Updated 5 months ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆38Updated 7 years ago
• olofk / i2c
  I2C controller core
  ☆16Updated 2 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆78Updated 4 years ago
• dawsonjon / Chips-Demo
  Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
  ☆15Updated 7 years ago
• abnoname / iceZ0mb1e
  FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
  ☆57Updated 2 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆94Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆68Updated 2 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 5 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆148Updated 7 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆116Updated 2 years ago
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆25Updated 4 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆120Updated 3 years ago
• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated this week
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆35Updated 2 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆61Updated 6 years ago
• kuopinghsu / biriscv
  biRISC-V - 32-bit dual issue RISC-V CPU Software Environment
  ☆11Updated 3 years ago
• grantae / mips32r1_core
  A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
  ☆18Updated 9 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated last month