fallen / tinycpuLinks
Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
☆35Updated 13 years ago
Alternatives and similar repositories for tinycpu
Users that are interested in tinycpu are comparing it to the libraries listed below
Sorting:
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆20Updated 12 years ago
- CMod-S6 SoC☆43Updated 7 years ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- An Open Source configuration of the Arty platform☆132Updated last year
- A reimplementation of a tiny stack CPU☆85Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 5 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- turbo 8051☆29Updated 8 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- A 6800 CPU written in nMigen☆49Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Minimal microprocessor☆21Updated 8 years ago
- 8051 core☆109Updated 11 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆36Updated 3 years ago
- Collection of hardware description languages writings and code snippets☆28Updated 10 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- OpenRISC Tutorials☆46Updated last week
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- The OpenRISC 1000 architectural simulator☆75Updated 7 months ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 11 months ago
- Digital FM Radio Receiver for FPGA☆63Updated 9 years ago
- A 16-bit Hack CPU from scratch on FPGA.☆59Updated 5 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆31Updated 5 years ago