Alternatives and similar repositories for digilent-vivado-scripts:

Users that are interested in digilent-vivado-scripts are comparing it to the libraries listed below

• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆53Updated last month
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆68Updated 3 months ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆92Updated this week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆94Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆129Updated 2 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆50Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆128Updated last month
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆35Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆110Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆135Updated this week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated 2 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆64Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆117Updated last week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• verilator / example-systemverilog
  ☆36Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 3 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆101Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated last month
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆154Updated last year
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆59Updated last week