[FCCM 2026] Official repository for LUT-LLM: Efficient Language Model Inference with Memory-based Computation on FPGAs
☆57Apr 12, 2026Updated 6 months ago
Alternatives and similar repositories for LUT-LLM
Users that are interested in LUT-LLM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Composable HLS library for rapid development of LLM accelerators. FlexLLM enables spatial-temporal hybrid architectures, with parameteriz…☆33Aug 17, 2026Updated 2 months ago
- [DATE'25, ICCAD'25] An embedded FPGA-based LLM accelerator capable of supporting Llama2-7B☆220Jul 30, 2026Updated 2 months ago
- ☆16May 23, 2024Updated 2 years ago
- A compiler for lowering quantized ML models to optimized AMD AI Engine (AIE) firmware.☆26Updated this week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆75Aug 1, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆23Aug 24, 2025Updated last year
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆41Nov 13, 2025Updated 11 months ago
- [FCCM 2025] Code Samples for InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs☆15Mar 26, 2025Updated last year
- ☆100Jun 25, 2026Updated 3 months ago
- DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU.☆29Nov 26, 2025Updated 10 months ago
- CODO: An Automated Compiler for Comprehensive Dataflow Optimization☆41Jun 3, 2026Updated 4 months ago
- TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs [FPGA2026]☆40Mar 11, 2026Updated 7 months ago
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆67Mar 8, 2026Updated 7 months ago
- A research shell for Alveo V80☆53Oct 16, 2026Updated last week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Mar 16, 2022Updated 4 years ago
- ☆29Jun 10, 2019Updated 7 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 7 years ago
- End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference☆62Jul 29, 2026Updated 2 months ago
- Virtual Joystick for LVGL☆20Feb 20, 2025Updated last year
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆20Dec 29, 2024Updated last year
- Open-source AI acceleration on FPGA: from ONNX to RTL☆62Oct 9, 2026Updated 2 weeks ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆20Feb 17, 2022Updated 4 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆390Jan 20, 2025Updated last year
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 5 months ago
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆26Dec 29, 2024Updated last year
- uIP 0.9 PicoSoC/PicoRV32 port☆11Apr 7, 2018Updated 8 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆78Dec 19, 2025Updated 10 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆153Jan 20, 2025Updated last year
- Allo Accelerator Design and Programming Framework (PLDI'24)☆414Oct 12, 2026Updated last week
- Accelerate multihead attention transformer model using HLS for FPGA☆13Dec 7, 2023Updated 2 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verilog re-implementation of the famous CAPCOM arcade game☆29Jan 25, 2019Updated 7 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 7 months ago
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated 2 months ago
- ☆12Jun 4, 2021Updated 5 years ago
- RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.☆20Oct 6, 2026Updated 2 weeks ago
- ☆42Mar 28, 2024Updated 2 years ago
- Artifact for Oaken: Fast and Efficient LLM Serving with Online-Offline Hybrid KV Cache Quantization☆20May 9, 2025Updated last year