Xilinx / AVEDLinks
Alveo Versal Example Design
☆41Updated 4 months ago
Alternatives and similar repositories for AVED
Users that are interested in AVED are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆20Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- ☆58Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆110Updated last year
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- ☆23Updated 4 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 5 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆15Updated 4 years ago
- ☆26Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 8 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Distributed Accelerator OS☆62Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆75Updated 10 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 9 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago