Xilinx / PYNQ-MetadataLinks
PYNQ-Metadata provides an abstract description of reconfigurable system designs.
☆8Updated last month
Alternatives and similar repositories for PYNQ-Metadata
Users that are interested in PYNQ-Metadata are comparing it to the libraries listed below
Sorting:
- PYNQ Composabe Overlays☆73Updated last year
- Public release☆57Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated 2 months ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 11 months ago
- AMD University Program HLS tutorial☆99Updated 9 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- ☆87Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆87Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆53Updated 10 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆65Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- ☆14Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 6 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆111Updated last week
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated 2 years ago
- ☆46Updated last year