Xilinx / PYNQ-BOT
☆25Updated 6 years ago
Related projects: ⓘ
- ☆23Updated this week
- PYNQ Composabe Overlays☆63Updated 3 months ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆101Updated 6 years ago
- ☆86Updated 4 years ago
- Pynq projects and guides☆27Updated 6 years ago
- Updated version of the XUP Workshops☆17Updated 6 years ago
- Board files to build Ultra 96 PYNQ image☆150Updated last week
- ☆82Updated 4 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆66Updated 6 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆25Updated 4 years ago
- ☆58Updated 5 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆38Updated 2 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆92Updated last year
- PYNQ, Neural network Language model, Overlay☆100Updated 5 years ago
- Design contest for DAC 2018☆17Updated 6 years ago
- Python package which accelerates OpenCV image filtering functions for the PYNQ framework☆46Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆47Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆62Updated last year
- Convolution Neural Network of vgg19 model in verilog☆42Updated 6 years ago
- A multi-board Extended Kalman Filter (EKF)☆28Updated 5 years ago
- ☆19Updated 2 years ago
- ☆43Updated 6 years ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆73Updated 11 months ago
- Caffe to VHDL☆66Updated 4 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆20Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆90Updated 5 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆96Updated 4 years ago
- This project is trying to create a base vitis platform to run with DPU☆48Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆103Updated 7 years ago
- The Verilog source code for DRUM approximate multiplier.☆26Updated last year