Alternatives and similar repositories for PYNQ_image

Users that are interested in PYNQ_image are comparing it to the libraries listed below

• hackwa / pynqfire
  Python FIR Filter Package for Xilinx Pynq Board
  ☆28Updated 7 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆18Updated 8 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆195Updated 6 years ago
• cfelton / rhea
  A collection of MyHDL cores and tools for complex digital circuit design
  ☆86Updated 6 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆49Updated 6 years ago
• DigilentInc / vivado-library
  ☆35Updated 7 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆182Updated 7 months ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆70Updated 4 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• Avnet / hdl
  ☆113Updated 4 months ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆49Updated 6 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 2 weeks ago
• fpgadeveloper / microzed-axi-dma
  Demonstration of the AXI DMA engine on the MicroZed
  ☆26Updated 4 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• Digilent / ZYBO
  ☆63Updated 8 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆171Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆103Updated 7 years ago