Alternatives and similar repositories for fpga_readings

Users that are interested in fpga_readings are comparing it to the libraries listed below

• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆331Updated 9 months ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆132Updated 4 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆387Updated 2 weeks ago
• fpgasystems / Coyote
  Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…
  ☆305Updated this week
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆285Updated this week
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆269Updated 9 months ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆219Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆341Updated this week
• Xilinx / Vivado-Design-Tutorials
  ☆234Updated 2 months ago
• Xilinx / XilinxBoardStore
  ☆303Updated last week
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆110Updated 5 years ago
• subbdue / systemverilog.io
  Code used in
  ☆198Updated 8 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆154Updated 2 months ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆397Updated last month
• ucsdsysnet / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆201Updated last year
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆369Updated 9 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆109Updated 2 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆176Updated 6 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆256Updated 5 months ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆244Updated 6 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 9 months ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆175Updated 2 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆180Updated last month
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆114Updated 3 years ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated 3 weeks ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆202Updated 3 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆141Updated last year
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆88Updated 5 months ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆167Updated last year