lastweek / fpga_readingsLinks
Recipe for FPGA cooking
☆306Updated last year
Alternatives and similar repositories for fpga_readings
Users that are interested in fpga_readings are comparing it to the libraries listed below
Sorting:
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆384Updated 3 months ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆132Updated 4 years ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆292Updated 2 weeks ago
- Open source FPGA-based NIC and platform for in-network compute☆198Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆257Updated 4 months ago
- Code used in☆197Updated 8 years ago
- ☆228Updated 2 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆283Updated last week
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆329Updated 8 months ago
- 100 Gbps TCP/IP stack for Vitis shells☆219Updated last year
- Example designs for FPGA Drive FMC☆265Updated 9 months ago
- ☆299Updated last week
- Build Customized FPGA Implementations for Vivado☆341Updated this week
- PCI express simulation framework for Cocotb☆179Updated last month
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- RISC-V Integration for PYNQ☆176Updated 6 years ago
- VNx: Vitis Network Examples☆154Updated last month
- Vitis HLS LLVM source code and examples☆396Updated 2 weeks ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆306Updated 3 weeks ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- SDAccel Development Environment Tutorials☆111Updated 5 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 8 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆141Updated last year
- Verilog Configurable Cache☆184Updated 10 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- Chisel examples and code snippets☆258Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 10 months ago
- Connectal is a framework for software-driven hardware development.☆174Updated last year