UFUG2601-CPP-Programming / Lab

Related projects: ⓘ

• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆12Updated 2 months ago
• fangwenji / tacas23-wasim
  ☆12Updated last year
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆15Updated 2 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆15Updated 8 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆16Updated 3 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆14Updated this week
• pku-dasys / easymac
  ☆15Updated 2 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆28Updated 3 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆45Updated 2 months ago
• amahzoon / genmul
  ☆14Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆22Updated 3 weeks ago
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆9Updated 3 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆20Updated 2 months ago
• cure-lab / DeepGate2
  ☆14Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆17Updated 11 months ago
• zshi0616 / python-deepgate
  ☆18Updated 2 months ago
• pku-liang / ksim
  ☆30Updated 5 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆18Updated 4 months ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆11Updated last year
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆16Updated 5 months ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆31Updated last year
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆20Updated 3 years ago
• iscas-tis / CHA
  ☆14Updated 2 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆37Updated 11 months ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆11Updated 3 years ago
• pku-liang / Cement
  A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.
  ☆11Updated 6 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆51Updated 2 weeks ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆16Updated last year
• efeslab / hardware-bugbase
  ☆16Updated 3 months ago
• gpt4rtl / AutoSVA2
  ☆12Updated 10 months ago