Alternatives and similar repositories for ABCPaperCheck

Users that are interested in ABCPaperCheck are comparing it to the libraries listed below

• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆28Updated last month
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆19Updated 2 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆33Updated 11 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆49Updated 5 months ago
• nbulsi / also
  A logic synthesis tool
  ☆74Updated this week
• zshi0616 / python-deepgate
  ☆22Updated last year
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆12Updated 2 years ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 6 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆19Updated 2 months ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆31Updated 7 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 3 weeks ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 11 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆29Updated 3 weeks ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆28Updated 2 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆79Updated 3 weeks ago
• Entropy-xcy / sns
  ☆18Updated 2 years ago
• SPbSAT / cirbo
  ☆22Updated 2 weeks ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆199Updated last month
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆22Updated 2 months ago
• lnis-uofu / ML-Mapper
  ☆11Updated 2 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆17Updated 2 years ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆27Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated last month