RongyeL / easy_axi
Learn the basics of AXI against the code and protocol
☆9Updated last year
Related projects ⓘ
Alternatives and complementary repositories for easy_axi
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆31Updated 3 months ago
- AXI总线连接器☆91Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago
- CPU Design Based on RISCV ISA☆76Updated 5 months ago
- syn script for DC Compiler☆12Updated 2 years ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- ☆19Updated 10 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆11Updated 6 months ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- Convolutional Neural Network RTL-level Design☆34Updated 3 years ago
- ☆12Updated 10 months ago
- ☆93Updated 4 years ago
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆121Updated 2 weeks ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆127Updated last year
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- ☆54Updated 4 years ago
- ☆26Updated 5 years ago
- IC Verification & SV Demo☆45Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆167Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆127Updated 5 months ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated last week
- AXI协议规范中文翻译版☆132Updated 2 years ago
- Open IP in Hardware Description Language.☆17Updated last year
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆70Updated 3 years ago
- IC implementation of Systolic Array for TPU☆152Updated last month
- some interesting demos for starters☆61Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆118Updated 7 months ago