artecs-group / PERCIVALLinks
Open-Source Posit RISC-V Core with Quire Capability
☆68Updated 10 months ago
Alternatives and similar repositories for PERCIVAL
Users that are interested in PERCIVAL are comparing it to the libraries listed below
Sorting:
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- ☆120Updated 4 months ago
- high-performance RTL simulator☆184Updated last year
- The specification for the FIRRTL language☆62Updated 2 weeks ago
- ☆59Updated 3 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆168Updated this week
- ☆89Updated last week
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆127Updated last week
- Next generation CGRA generator☆118Updated this week
- Open-source RTL logic simulator with CUDA acceleration☆243Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆78Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- Chisel RISC-V Vector 1.0 Implementation☆123Updated 2 months ago
- ☆58Updated 8 months ago
- ☆70Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- The multi-core cluster of a PULP system.☆109Updated last month
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 8 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Raptor end-to-end FPGA Compiler and GUI☆91Updated last year
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Updated 7 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- FPGA tool performance profiling☆103Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆205Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week