Alternatives and similar repositories for PERCIVAL:

Users that are interested in PERCIVAL are comparing it to the libraries listed below

• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆68Updated 5 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆109Updated this week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆119Updated 8 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 9 months ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆37Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆90Updated this week
• pulp-platform / redmule
  ☆42Updated this week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆99Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆152Updated 8 months ago
• ChenJianyunp / Posit32-2-exact-multiply-accumulator
  This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
  ☆16Updated 7 years ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆34Updated 3 years ago
• bsc-loca / sargantana
  ☆82Updated 10 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆55Updated 5 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆70Updated this week
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆37Updated 5 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆67Updated this week
• chipsalliance / fpga-interchange-schema
  ☆54Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆78Updated last week
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆36Updated 10 months ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆17Updated 2 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆127Updated last month
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 3 months ago