Alternatives and similar repositories for PERCIVAL

Users that are interested in PERCIVAL are comparing it to the libraries listed below

• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• bsc-loca / sargantana
  ☆114Updated 3 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆182Updated last year
• pulp-platform / redmule
  ☆88Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆121Updated last month
• chipsalliance / fpga-interchange-schema
  ☆57Updated 3 years ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆238Updated last month
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆124Updated last week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆113Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆116Updated this week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆126Updated last year
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆45Updated 7 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆76Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆103Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆115Updated last year
• ChenJianyunp / Posit32-2-exact-multiply-accumulator
  This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
  ☆17Updated 7 years ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆168Updated last month
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated 3 weeks ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆107Updated 3 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆179Updated 6 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 8 months ago