artecs-group / PERCIVALLinks
Open-Source Posit RISC-V Core with Quire Capability
☆66Updated 8 months ago
Alternatives and similar repositories for PERCIVAL
Users that are interested in PERCIVAL are comparing it to the libraries listed below
Sorting:
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Next generation CGRA generator☆115Updated this week
- high-performance RTL simulator☆178Updated last year
- ☆108Updated 2 months ago
- The specification for the FIRRTL language☆61Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Updated 7 years ago
- Open-source RTL logic simulator with CUDA acceleration☆222Updated 2 weeks ago
- ☆79Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- ☆56Updated 3 years ago
- ☆54Updated 6 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- FPGA tool performance profiling☆102Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆165Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated last week
- The multi-core cluster of a PULP system.☆108Updated 2 weeks ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 2 weeks ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆114Updated last year
- Chisel library for Unum Type-III Posit Arithmetic☆43Updated 6 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago