Alternatives and similar repositories for PERCIVAL

Users that are interested in PERCIVAL are comparing it to the libraries listed below

• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆72Updated 5 years ago
• ChenJianyunp / Posit32-2-exact-multiply-accumulator
  This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
  ☆16Updated 7 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆160Updated last year
• pulp-platform / redmule
  ☆65Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated last month
• bsc-loca / sargantana
  ☆104Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆105Updated last year
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆159Updated 2 weeks ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated last month
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆101Updated last month
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆88Updated 5 months ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆41Updated 2 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆56Updated 6 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆101Updated last week
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆41Updated last month
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆52Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆128Updated this week
• lana555 / dynamatic
  ☆86Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆111Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆86Updated last year