Alternatives and similar repositories for coatcheck:

Users that are interested in coatcheck are comparing it to the libraries listed below

• daniellustig / pipecheck
  ☆19Updated 10 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆21Updated 6 years ago
• ymanerka / ccicheck
  ☆9Updated 9 years ago
• ymanerka / pipeproof
  PipeProof
  ☆11Updated 5 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆37Updated 2 weeks ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆12Updated 4 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆32Updated 3 years ago
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆12Updated last month
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 5 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆24Updated 6 months ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆79Updated last week
• ctrippel / TriCheck
  ☆14Updated 7 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆43Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆65Updated this week
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆18Updated 2 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆70Updated 4 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• iscas-tis / CHA
  ☆18Updated 9 months ago
• aakahlow / gem5Valid_Haswell
  ☆18Updated 5 years ago
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆13Updated last month
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• ucb-bar / midas-release
  MIDAS Public Release
  ☆9Updated 6 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 5 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated last week