Alternatives and similar repositories for PynqRadio:

Users that are interested in PynqRadio are comparing it to the libraries listed below

• marsiau / PYNQ-RTL-SDR
  A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR
  ☆20Updated 5 years ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆91Updated 8 years ago
• MicroPhase / antsdr-pynq
  pynq framework for antsdr
  ☆34Updated 9 months ago
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆53Updated last month
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆30Updated 8 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆42Updated 10 months ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆73Updated 8 months ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆67Updated 7 years ago
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆73Updated 4 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆60Updated 2 years ago
• daveshah1 / RFToolSDR
  AD9361 based USB3 SDR
  ☆101Updated 7 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆109Updated 4 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆81Updated 2 years ago
• controlpaths / cp_som_one
  Artix7 SOM
  ☆15Updated 5 months ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• DiegoRosales / VHDL_Modules
  VHDL Modules
  ☆24Updated 9 years ago
• hamsternz / second_order_sigma_delta_DAC
  A comparison of 1st and 2nd order sigma delta DAC for FPGA
  ☆55Updated 4 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆27Updated 6 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆21Updated last year
• catkira / CIC
  HDL code for a complex multiplier with AXI stream interface
  ☆16Updated 2 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆113Updated last year
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆86Updated 5 months ago
• Tobias-DG3YEV / RA-Sentinel
  FPGA based WiFi Intrusion detection system
  ☆18Updated this week
• laurencebarker / Saturn
  Saturn SDR Radio: Xilinx FPGA and Raspberry Pi 4 CM
  ☆36Updated this week
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆102Updated last year
• catkira / DDS
  HDL code for a DDS (direct digital synthesizer) with AXI stream interface
  ☆18Updated last year
• xil-se / SX1257-PMOD
  ☆15Updated 5 years ago
• controlpaths / blog
  Projects published on controlpaths.com and hackster.io
  ☆40Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆54Updated this week