Muhazam-Mustapha / SqrtCORDIC
A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.
☆13Updated 3 years ago
Related projects: ⓘ
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆11Updated 8 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆51Updated last month
- Pipeline FFT Implementation in Verilog HDL☆71Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆47Updated 8 years ago
- Cortex M0 based SoC☆68Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- upgrade to e203 (a risc-v core)☆36Updated 4 years ago
- 3×3脉动阵列乘法器☆33Updated 5 years ago
- FFT generator using Chisel☆55Updated 2 years ago
- IC implementation of Systolic Array for TPU☆137Updated 6 months ago
- 视频旋转（2019FPGA大赛）☆28Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆79Updated 3 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。☆37Updated 9 months ago
- Reed Solomon Encoder and Decoder Digital IP☆15Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆65Updated 5 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆38Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 5 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆72Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆152Updated last year
- ☆57Updated last year
- AXI DMA 32 / 64 bits☆95Updated 10 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆16Updated 9 months ago
- CNN accelerator implemented with Spinal HDL☆128Updated 7 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆46Updated last year
- A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、…☆122Updated last year
- AXI总线连接器☆89Updated 4 years ago
- 2023集创赛国二，紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆108Updated 5 months ago
- commit rtl and build cosim env☆35Updated 5 months ago
- ☆83Updated 4 years ago
- AHB DMA 32 / 64 bits☆48Updated 10 years ago