Alternatives and similar repositories for fir-filter-fpga

Users that are interested in fir-filter-fpga are comparing it to the libraries listed below

• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆146Updated 4 years ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆172Updated 4 months ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆44Updated 6 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated 2 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆156Updated last year
• FPGADude / Digital-Design
  Verilog HDL files
  ☆153Updated last year
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆216Updated 4 months ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆116Updated 3 years ago
• AngeloJacobo / FPGA_RealTime_and_Static_Sobel_Edge_Detection
  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
  ☆64Updated 3 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆76Updated 3 years ago
• aseddin / ece_3300
  ECE 3300 HDL Code
  ☆58Updated 2 years ago
• daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
  Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
  ☆14Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆96Updated 2 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆47Updated last year
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆392Updated last year
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆141Updated 3 months ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆34Updated 2 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆67Updated 3 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆113Updated 3 months ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆53Updated last year
• tms4517 / 2D-Systolic-Array-Multiplier
  2D Systolic Array Multiplier
  ☆20Updated last year
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆132Updated 6 years ago
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆32Updated 8 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆20Updated last year
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆116Updated 3 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆63Updated 10 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆156Updated 2 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆143Updated 11 years ago