darthsider / UART

Related projects ⓘ

Alternatives and complementary repositories for UART

• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆56Updated 3 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆36Updated 3 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆16Updated 3 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆16Updated 3 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆26Updated 4 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆20Updated 2 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆28Updated 4 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆34Updated 4 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆25Updated 4 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆16Updated 4 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆27Updated last year
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆54Updated last year
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆42Updated 8 months ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆29Updated 4 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆47Updated 4 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆26Updated 6 years ago
• designsolver / ahb3_uvm_tb
  AMBA 3 AHB UVM TB
  ☆34Updated 5 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆46Updated 3 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆26Updated 7 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆76Updated 2 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆71Updated last year
• Lampro-Mellon / apb-uart-uvm-env
  ☆34Updated last year
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆34Updated 4 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆47Updated 3 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆18Updated 4 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆28Updated 2 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆23Updated 3 weeks ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆22Updated 5 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆51Updated 7 years ago