yueyang2000 / riscv-cpu
RISC-V multi cycle CPU. Project of Computer Organization (THU 2020)
☆15Updated 2 years ago
Alternatives and similar repositories for riscv-cpu:
Users that are interested in riscv-cpu are comparing it to the libraries listed below
- Mips五级流水线CPU☆37Updated 2 years ago
- 清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期,造台计算机」☆13Updated 2 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆126Updated 8 months ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆72Updated 5 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆122Updated 4 years ago
- 清华大学计算机系零字班计算机组成原理大实验作业。☆21Updated 2 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆42Updated 4 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆34Updated 3 years ago
- 计算机组成原理的实验,包括单周期CPU和五级流水线CPU的verilog实现☆35Updated 3 years ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆126Updated 5 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆76Updated last year
- NSCSCC 信息整合☆232Updated 4 years ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆34Updated 4 years ago
- MIPS 57条 指令五级流水线cpu (verilog实现+详细注释)☆11Updated 3 years ago
- 清华大学2021操作系统实验代码☆16Updated 3 years ago
- 基于龙芯 OpenMIPS 实现一个具有 89 条指令的五级流水 CPU,使用 Verilog 语言,使用哈佛结构,包括逻辑移位指令、乘除法指令、加载存储指令、转移指令、协处理器访问指令以及异常相关在内的共89条指令。能够处理数据相关,包含流水线暂停以及延迟槽☆20Updated 5 years ago
- 单周期 8指令 MIPS32CPU☆89Updated 2 years ago
- NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)☆60Updated 11 months ago
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- ☆32Updated last year
- Introduction to Computer Systems (II), Spring 2021☆50Updated 3 years ago
- ☆34Updated 5 years ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆44Updated 2 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆38Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- 哈工大2023处理器设计与计算机体系结构实验☆18Updated 6 months ago
- Verilog实现单周期非流水线32位RISCV指令集(45条)CPU☆38Updated 4 years ago
- riscv指令集,单周期以及五级流水线CPU☆43Updated 2 months ago
- Chongqing University 2020 NSCSCC☆28Updated 4 years ago
- 用verilog实现单周期cpu和流水线☆20Updated 5 years ago