Alternatives and similar repositories for RISC_V-pipeline

Users that are interested in RISC_V-pipeline are comparing it to the libraries listed below

• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆29Updated 2 years ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆82Updated 5 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆290Updated 7 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated last month
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆23Updated 2 years ago
• yyNoBug / RISCV-CPU
  A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…
  ☆9Updated 5 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 8 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated 11 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆203Updated 3 weeks ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆116Updated 12 years ago
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• OpenXiangShan / GEM5
  ☆86Updated last week
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆110Updated last week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆89Updated 3 months ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆146Updated 6 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆137Updated last year
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆20Updated 7 years ago